BSc CSIT (TU) Science Microprocessor (BSc CSIT, CSC162) Question Paper 2081 Nepal

Data Transfer Schemes of a Microprocessor

Data transfer between the microprocessor (or memory) and I/O devices is handled by three main schemes.

1. Programmed I/O

In programmed I/O the CPU is fully responsible for the transfer. The processor executes IN/OUT (or memory-mapped MOV) instructions and, before transferring each byte, it repeatedly polls the device status flag (busy/ready).

• The CPU stays in a wait/polling loop until the device is ready.
• Simple to implement, needs no extra hardware.
• Disadvantage: CPU time is wasted busy-waiting; throughput is low. Suitable only for slow devices and small data.

2. Interrupt-Driven I/O

Here the device, when ready, sends an interrupt request (INTR/NMI) to the CPU instead of being polled.

• The CPU does useful work meanwhile. On interrupt, it finishes the current instruction, saves the flags and return address on the stack, and jumps to the Interrupt Service Routine (ISR) that transfers the data.
• After the ISR, IRET restores the context and the CPU resumes.
• Advantage: No busy-waiting, so the CPU is used efficiently.
• Disadvantage: Each byte still passes through the CPU; context-switching overhead per transfer limits speed for high-volume data.

3. Direct Memory Access (DMA)

For large, fast block transfers a dedicated DMA controller (e.g., 8237) moves data directly between the I/O device and memory without the CPU handling each byte.

• The device asserts a DMA request (DRQ); the DMA controller raises HOLD, the CPU completes the current bus cycle, floats its buses and replies HLDA, surrendering the system bus.
• The DMA controller then supplies addresses and control signals to transfer a whole block, and interrupts the CPU when finished.
• Advantage: Very high transfer rate, CPU free during the transfer.
• Disadvantage: Needs extra hardware (DMA controller) and the CPU is idle (cannot use the bus) during the transfer.

Comparison

Conclusion: Programmed I/O is simplest but wastes CPU time; interrupt-driven I/O removes the wait but still routes data through the CPU; DMA gives the highest speed for large blocks by bypassing the CPU entirely.

8253/8254 Programmable Interval Timer (PIT)

The 8253/8254 is a programmable peripheral that generates accurate time delays, square waves, rate generators and event counts under software control, relieving the CPU of timing tasks. The 8254 is an enhanced version of the 8253 (higher clock up to 8/10 MHz and a read-back command).

Architecture

• Three independent 16-bit counters — Counter 0, Counter 1, Counter 2 — each with its own CLK, GATE (enable) input and OUT output.
• Data Bus Buffer (8-bit, D0–D7) to interface with the system data bus.
• Read/Write Logic controlled by RD, WR, CS, and address lines A1A0 (A1A0 = 00, 01, 10 select Counter 0/1/2; 11 selects the Control Word Register).
• Each counter can be programmed as BCD or binary and loaded with an initial count; it decrements on each clock pulse.

Operating Modes (selected via the control word)

Control Word Format

SC1 SC0 RW1 RW0 M2 M1 M0 BCD — selects counter, read/write sequence (LSB/MSB), mode (0–5) and BCD/binary.

Applications

• Generating time delays and periodic timer interrupts (e.g., the system clock tick in the IBM PC).
• Square-wave / baud-rate generation for serial communication.
• Frequency division and event/pulse counting.
• Real-time clock, DRAM refresh timing, and speaker tone generation.

Marking summary: Architecture + diagram description (3), six modes (4), control word + applications (3).

Assembly Program to Sort an Array in Ascending Order

Algorithm Used — Bubble Sort

Bubble sort repeatedly steps through the list, compares each pair of adjacent elements and swaps them if they are in the wrong order. After each full pass the largest unsorted element "bubbles" to its correct position. For n elements it needs at most n-1 passes; here we use a simple fixed n-1 outer loop with an inner comparison loop.

8086 Assembly Program (sorts a byte array)

.MODEL SMALL
.DATA
    ARR   DB 25H, 12H, 56H, 03H, 49H, 18H
    N     EQU 6                 ; number of elements
.CODE
MAIN PROC
    MOV AX, @DATA
    MOV DS, AX

    MOV CX, N-1                 ; outer loop count = n-1 passes
OUTER:
    MOV SI, OFFSET ARR          ; point to start of array
    MOV DX, CX                  ; inner loop count (passes shrink)
INNER:
    MOV AL, [SI]                ; AL = current element
    CMP AL, [SI+1]              ; compare with next element
    JBE NOSWAP                  ; if AL <= next, no swap (unsigned)
    ; swap the two adjacent bytes
    MOV BL, [SI+1]
    MOV [SI+1], AL
    MOV [SI], BL
NOSWAP:
    INC SI                      ; move to next pair
    DEC DX
    JNZ INNER                   ; repeat inner loop
    LOOP OUTER                  ; repeat outer loop (decrements CX)

    MOV AH, 4CH                 ; terminate program
    INT 21H
MAIN ENDP
END MAIN

Working

1. DS is loaded with the data segment.
2. CX holds the number of passes (n-1).
3. In each pass SI scans the array; CMP AL,[SI+1] with JBE keeps the smaller element first (ascending). If AL > next, the two bytes are swapped.
4. After all passes the array ARR is sorted in ascending order.

(For signed numbers replace JBE with JLE.)

Marking summary: Correct algorithm explanation (3), correct working program with comments (5), explanation of swap/loop logic (2).

Accumulator vs General-Purpose Registers

In short: the accumulator is a special register that automatically holds operands and results of ALU/I-O operations, whereas general-purpose registers are flexible scratch registers used for holding data, counters and addresses.

Maximum Memory Addressable by the 8086

The 8086 can address a maximum of 1 MB ($2^{20}$ = 1,048,576 bytes) of physical memory.

Reason: The 8086 has a 20-bit address bus (A0–A19). The number of distinct addresses is $2^{20} = 1\,048\,576 = 1\,\text{MB}$, and since memory is byte-addressable, it can access 1 MB of memory.

The 8086 internally uses 16-bit registers, which alone could address only $2^{16} = 64$ KB. To reach the full 1 MB it uses memory segmentation: a 16-bit segment register is shifted left by 4 bits and added to a 16-bit offset to form the 20-bit physical address:

This 20-bit result spans the entire 1 MB address space.

Role of the 8253 Timer

The 8253 is a Programmable Interval Timer (PIT) used as a peripheral with the microprocessor to perform timing and counting functions in hardware, freeing the CPU from software delay loops.

Its main roles are:

• Generating accurate time delays and periodic timer interrupts (e.g., the system clock tick).
• Square-wave / clock generation for baud-rate generation in serial communication.
• Rate generation (divide-by-N) and frequency division.
• Event and pulse counting of external signals on the GATE/CLK inputs.

It contains three independent 16-bit programmable counters, each programmable in one of six modes (Mode 0–5) and in binary or BCD, configured through a control word. This provides hardware timing far more precise and CPU-efficient than software delay routines.

Conditional and Unconditional Jump Instructions

Jump instructions transfer program control to a different address (change the value of IP), implementing branching and loops.

Unconditional Jump

The JMP instruction transfers control to the target address always, regardless of any flag. It is used to skip code, form infinite loops, or implement goto-style branching.

JMP LABEL      ; always jumps to LABEL

Types: near (within segment, modifies IP) and far (between segments, modifies CS:IP); also direct and indirect.

Conditional Jump

A conditional jump transfers control only if a specified condition (flag state) is true; otherwise execution continues with the next instruction. The condition is set by the previous CMP, arithmetic or logic instruction (testing flags ZF, CF, SF, OF, PF).

CMP AX, BX
JE  EQUAL      ; jump if ZF = 1 (AX == BX)
JG  GREATER    ; jump if AX > BX (signed)
JC  CARRY      ; jump if carry flag set

Common conditional jumps: JZ/JE, JNZ/JNE, JC, JNC, JA/JAE, JB/JBE, JG/JGE, JL/JLE, JS, JO. These are short jumps (±127 bytes).

Difference: JMP jumps unconditionally; conditional jumps jump only when their tested flag condition is satisfied, enabling decision-making and loops.

Function of the RESET Signal

The RESET input is used to initialize the microprocessor to a known starting state.

When the RESET signal is activated (held high for the required number of clock cycles in the 8086), the processor:

• Stops the currently executing program and aborts any operation.
• Clears/initializes internal registers — the flags, IP, DS, SS, ES and the instruction queue are cleared, and CS is set to FFFFH and IP to 0000H, so execution begins from physical address FFFF0H (the reset/boot vector).
• Disables interrupts (IF and TF cleared) until they are re-enabled by software.

Thus RESET forces the CPU to start program execution from a fixed, predefined location, which is where the bootstrap/start-up code is placed. It is used at power-on (power-on reset) and to recover the system from a hang.

Rotate and Shift Instructions

These instructions move the bits of an operand left or right; the difference is what happens to the bits shifted out.

Shift Instructions

In a shift, bits move out one end and 0 (or the sign bit) is brought in at the other end; bits shifted out go into the Carry Flag (CF).

• SHL / SAL – Shift/Arithmetic Shift Left: each bit moves left, 0 enters the LSB, MSB goes to CF. Equivalent to multiply by 2.
• SHR – Shift Right (logical): each bit moves right, 0 enters the MSB, LSB goes to CF. Equivalent to unsigned divide by 2.
• SAR – Arithmetic Shift Right: same as SHR but the sign bit (MSB) is preserved, giving signed divide by 2.

Rotate Instructions

In a rotate, bits shifted out at one end are fed back in at the other end; no bits are lost.

• ROL – Rotate Left: MSB rotates into LSB (and into CF).
• ROR – Rotate Right: LSB rotates into MSB (and into CF).
• RCL – Rotate through Carry Left: bits rotate through CF (CF is part of the loop).
• RCR – Rotate through Carry Right: bits rotate right through CF.

Example: MOV AL, 81H then ROL AL, 1 → AL = 03H, CF = 1 (the MSB wrapped to LSB).

Difference: Shifts discard the bit that leaves the register (replacing with 0/sign), while rotates circulate the bit back into the operand. The count is given as 1 or in CL.

Interrupt Priority

Interrupt priority is the predefined ordering that decides which interrupt is serviced first when two or more interrupt requests occur at the same time (or while another ISR is running).

• The CPU/interrupt controller compares the priorities and services the higher-priority interrupt first; lower-priority requests are held pending or kept waiting until the higher one finishes.
• It also determines whether an interrupt can preempt (nest within) a currently executing ISR — a higher-priority interrupt can interrupt a lower-priority service routine.

In the 8086, the fixed priority order (highest to lowest) is roughly: divide-by-zero / internal exceptions and software interrupts (INT n) → NMI (non-maskable) → INTR (maskable) → single-step. NMI always has higher priority than the maskable INTR.

In systems with the 8259A Programmable Interrupt Controller (PIC), priorities of the eight IR lines (IR0 highest … IR7 lowest in fixed mode) are programmable and can be rotated. Interrupt priority ensures time-critical and important events are handled promptly.

Synchronous vs Asynchronous Data Transfer

In short: synchronous transfer relies on a shared clock and fixed timing (fast, low overhead), while asynchronous transfer uses handshaking/start–stop signaling to coordinate devices of differing speeds (flexible, slower).

Use of INT and IRET Instructions

INT n (Software Interrupt)

INT n invokes a software interrupt — it calls the interrupt service routine whose number is n (n = 0–255). When executed, the processor:

1. Pushes the Flag register, then CS and IP onto the stack.
2. Clears the IF and TF flags (disabling further maskable interrupts and trace).
3. Fetches the new CS:IP of the ISR from the Interrupt Vector Table at memory address n × 4, and jumps there.

It is used to invoke operating system / BIOS services (e.g., INT 21H for DOS functions, INT 10H for video) and to handle exceptions.

IRET (Interrupt Return)

IRET is placed at the end of every interrupt service routine. It returns control to the interrupted program by performing the reverse of INT:

1. Pops IP, then CS, then the Flag register from the stack.

This restores the exact processor state (including the flags) that existed before the interrupt, so the main program resumes seamlessly. (Note: IRET restores flags, unlike a normal RET.)

Summary: INT n transfers control to an ISR via the vector table (saving flags and CS:IP); IRET restores them and resumes the interrupted program.