BSc CSIT (TU) Science Microprocessor (BSc CSIT, CSC162) Question Paper 2078 Nepal

Instruction Set of the 8086 Microprocessor

The instruction set is the complete collection of machine-level commands that a microprocessor can understand and execute. The 8086 instructions are grouped into the following functional categories.

1. Data Transfer Instructions

Move data between registers, memory and I/O ports without altering flags (except SAHF/POPF).

2. Arithmetic Instructions

Perform addition, subtraction, multiplication, division and affect status flags.

• ADD AX, BX, ADC (add with carry)
• SUB, SBB (subtract with borrow)
• INC, DEC
• MUL, IMUL (unsigned/signed multiply)
• DIV, IDIV
• CMP AX, BX (compare), NEG, AAA/DAA (ASCII/decimal adjust)

3. Logical Instructions

Bitwise operations and bit testing.

• AND, OR, XOR, NOT
• TEST (non-destructive AND that sets flags)
• Shifts: SHL, SHR, SAR
• Rotates: ROL, ROR, RCL, RCR

4. Branch (Program Control) Instructions

Alter the sequence of execution.

• Unconditional: JMP, CALL, RET
• Conditional: JZ, JNZ, JC, JNC, JG, JL, JE
• Loop: LOOP, LOOPE, LOOPNE
• Interrupt: INT n, INTO, IRET

5. Machine Control / Flag Control Instructions

Control processor operation and individual flags.

• STC/CLC (set/clear carry), STD/CLD, STI/CLI
• NOP (no operation), HLT (halt)
• WAIT, LOCK, ESC

Conclusion

These five groups together let the 8086 transfer data, compute results, perform logic, control program flow and manage the processor, forming a complete, general-purpose instruction set.

Instruction Cycle

The instruction cycle is the complete sequence of steps the CPU performs to fetch, interpret and execute a single instruction. It repeats continuously while the processor runs and consists of three basic phases.

1. Fetch Cycle

The processor reads the instruction opcode from memory:

• The contents of the program counter / instruction pointer (IP with CS) are placed on the address bus.
• A memory read is issued; the opcode is brought into the instruction register (or the 8086 prefetch queue).
• IP is incremented to point to the next instruction.

2. Decode Cycle

The control unit examines the opcode to determine:

• which operation is required,
• the addressing mode and the location of operands.

3. Execute Cycle

The processor performs the operation: it reads operands, the ALU computes the result, flags are updated and the result is written back to a register, memory or I/O port.

In the 8086, the BIU performs fetching (filling the 6-byte queue) while the EU decodes and executes, so fetch and execute overlap (pipelining).

Timing Diagram of a Memory Read Operation

A memory read is completed in one bus cycle of four T-states (T1–T4) using a clock (CLK).

• T1: The 8086 outputs the 20-bit address on the multiplexed AD0–AD15 and A16–A19 lines. ALE goes high to latch the address into an external latch (e.g., 74LS373); ALE then falls.
• T2: Address is removed; AD lines go to high impedance (turn-around). RD (read) is asserted low and the memory is selected. DT/R = 0 (receive), DEN is activated.
• T3: The selected memory places the data on the data bus. If memory is slow, the READY line is sampled; if low, wait states (Tw) are inserted between T3 and T4.
• T4: The 8086 reads the data on the falling edge, RD returns high and the bus cycle ends.

Description of waveform: CLK shows four cycles; ALE is a narrow pulse in T1; address is valid early in T1 and data appears on the bus during T3–T4; RD stays low from T2 to T4.

Conclusion

Every instruction = fetch + decode + execute, and each external memory read takes a 4-state bus cycle (extendable by wait states for slow memory).

Program: Largest Number in an Array of n Numbers (8086)

Logic

1. Assume the first element is the largest and load it into a register (AL).
2. Set a counter to n-1 and point SI to the next element.
3. Compare the current largest with the next element using CMP.
4. If the new element is greater, update the largest.
5. Decrement the counter and repeat using LOOP until all elements are checked.
6. Store the result. The largest survives because every element is compared against the running maximum.

Assembly Code (8086, byte data)

.MODEL SMALL
.DATA
    ARRAY   DB  23H, 45H, 12H, 78H, 56H   ; sample array
    N       EQU 5
    LARGEST DB  ?
.CODE
MAIN PROC
    MOV AX, @DATA
    MOV DS, AX

    LEA SI, ARRAY        ; SI -> first element
    MOV AL, [SI]         ; assume first element is largest
    MOV CX, N-1          ; compare remaining (n-1) elements
    INC SI               ; point to second element

NEXT:
    CMP AL, [SI]         ; largest vs current element
    JAE SKIP             ; if AL >= element, keep AL
    MOV AL, [SI]         ; else update largest
SKIP:
    INC SI
    LOOP NEXT            ; CX = CX-1, repeat until 0

    MOV LARGEST, AL      ; store result

    MOV AH, 4CH          ; terminate program
    INT 21H
MAIN ENDP
END MAIN

Result

After execution, LARGEST (and AL) holds 78H, the maximum value of the sample array. The algorithm runs in O(n) with a single pass through the array.

(For unsigned bytes use JAE; for signed numbers use JGE. For 16-bit word data, use MOV AX,[SI], ADD SI,2 and compare with AX.)

Macro vs Procedure

Summary: Use a macro for short sequences where speed matters and code-size growth is acceptable; use a procedure for longer routines where memory economy matters.

The ASSUME Directive

ASSUME is an assembler directive (not a CPU instruction) that tells the assembler which segment register points to which program segment. It lets the assembler generate the correct addresses/offsets but does not itself load the registers.

Syntax

ASSUME CS:CODE, DS:DATA, SS:STACK, ES:EXTRA

Use / Purpose

• Associates a segment register (CS, DS, SS, ES) with a logical segment name so the assembler knows where labels and variables reside.
• Allows the programmer to refer to variables by name; the assembler computes offsets relative to the assumed segment.
• Generates correct segment-override prefixes only when needed.

Important note

ASSUME only informs the assembler. The segment registers must still be physically loaded at run time, e.g.:

MOV AX, DATA
MOV DS, AX        ; actually load DS

(CS and IP are loaded automatically when the program starts.)

Tristate Logic

Tristate (three-state) logic is a logic-output arrangement in which a device output can be in one of three states instead of the usual two:

1. Logic 0 (low)
2. Logic 1 (high)
3. High-impedance (Hi-Z / floating) — the output is effectively disconnected from the bus.

The high-impedance state is selected by an enable/disable (control) input. When disabled, the device neither drives 0 nor 1, so it offers very high impedance and does not load the bus.

Why it is needed

In a microprocessor system many devices (CPU, memory, I/O) share common buses (address, data, control). Tristate logic allows only one device to drive the bus at a time while all others stay in Hi-Z, preventing bus contention. This is why the 8086 address/data lines and buffers (e.g., 74LS245) are tristate.

Function of the Queue in 8086

The 8086 has a 6-byte instruction queue maintained by the Bus Interface Unit (BIU). It implements instruction prefetching / pipelining.

Function

• While the Execution Unit (EU) is busy decoding and executing the current instruction (and not using the bus), the BIU fetches the next instruction bytes in advance and stores them in the queue.
• The EU then takes instructions directly from the queue instead of waiting for a memory fetch each time.

Benefits

• Overlaps fetch and execute (pipelining), increasing speed and using the bus efficiently.
• Reduces idle time of the processor.

Note

The queue is flushed (emptied) whenever a branch, jump, call, interrupt or return is taken, because the prefetched bytes are no longer the correct next instructions; fetching then restarts at the new address. (The 8088 uses a smaller 4-byte queue.)

Data Transfer Instructions of 8086

Data transfer instructions copy data between registers, memory and I/O without performing arithmetic/logic; they generally do not affect flags (except SAHF, POPF).

General-purpose transfer

• MOV — move data between register/memory/immediate
• XCHG — exchange contents of two operands
• XLAT — translate a byte using a look-up table

Stack operations

• PUSH, POP — store/retrieve a word on/from the stack
• PUSHF, POPF — push/pop the flag register

Input/Output

• IN, OUT — read from / write to an I/O port

Address-object transfer

• LEA — load effective address
• LDS, LES — load pointer with DS/ES

Flag transfer

• LAHF — load AH from flags
• SAHF — store AH into flags

Role of the BHE Signal

BHE stands for Bus High Enable ($\overline{BHE}$, active low) and is output by the 8086 on pin BHE/S7.

The 8086 has a 16-bit data bus organized as two 8-bit memory banks:

• Lower (even) bank — selected by address line A0 = 0
• Upper (odd) bank — selected by $\overline{BHE} = 0$

Function

$\overline{BHE}$ enables the high-order data byte (D15–D8, the odd/upper bank). Together with A0 it determines which bytes are transferred:

Thus $\overline{BHE}$ lets the 8086 access a single odd byte, a single even byte, or a full 16-bit word, supporting both byte and word operations.

MOV vs XCHG

Example: If AX = 10H, BX = 20H:

• After MOV AX, BX: AX = 20H, BX = 20H.
• After XCHG AX, BX: AX = 20H, BX = 10H.

Neither instruction affects the flags. XCHG needs no temporary register to swap two values.

Wait State

A wait state (Tw) is an extra clock period inserted into a bus cycle by the microprocessor to give slow memory or I/O devices more time to respond.

How it works

• A normal 8086 bus cycle is four T-states (T1–T4).
• The processor samples the READY input (usually during T3).
• If READY = 0 (device not ready), the 8086 inserts wait states (Tw) between T3 and T4, holding the bus signals steady.
• When the device pulls READY = 1, the processor completes T4 and finishes the read/write.

Purpose

Wait states synchronize the fast CPU with slow peripherals, ensuring valid data transfer without using costly fast memory. Each wait state equals one extra clock cycle, slightly reducing throughput. A circuit called a wait-state generator controls the READY line.

Based Indexed Addressing Mode

In based-indexed addressing, the effective address (offset) of the operand is formed by adding a base register and an index register (and optionally a displacement).

Effective address

• Base register: BX or BP
• Index register: SI or DI
• Default segment: DS (with BX) or SS (with BP)

Example

MOV AX, [BX + SI]          ; EA = BX + SI
MOV AX, [BX + DI + 10H]    ; EA = BX + DI + displacement

If BX = 1000H, SI = 0020H, DS = 2000H, then for MOV AX, [BX+SI]:

• Offset (EA) $= 1000H + 0020H = 1020H$
• Physical address $= (DS \times 10H) + EA = 20000H + 1020H = 21020H$.

Use

This mode is ideal for accessing two-dimensional arrays, tables and records, where the base register points to the start of the structure and the index register selects an element. It is highly flexible because both registers can vary at run time.