BSc CSIT (TU) Science Microprocessor (BSc CSIT, CSC162) Question Paper 2080 Nepal

Architecture of the 8086 with Pipelining

The 8086 is a 16-bit microprocessor that internally splits its work into two independent functional units so that fetching and execution can overlap. This overlap is the essence of its pipelining.

1. Bus Interface Unit (BIU)

The BIU handles all transactions with memory and I/O.

• Contains the segment registers (CS, DS, SS, ES) and the Instruction Pointer (IP).
• Computes the 20-bit physical address as $\text{Physical Address} = (\text{Segment} \times 16) + \text{Offset}$, giving a 1 MB address space.
• Contains the 6-byte instruction queue (prefetch queue).
• Performs instruction fetch, operand read/write, and bus control.

2. Execution Unit (EU)

The EU decodes and executes instructions.

• Contains the ALU, flag register, general-purpose registers (AX, BX, CX, DX), pointer/index registers (SP, BP, SI, DI), and the control/timing logic and instruction decoder.
• The EU has no connection to the system bus; whenever it needs data, it requests the BIU.

3. Pipelining via Instruction Queuing

In earlier processors (e.g. 8085) fetch and execute are sequential, so the bus is idle while the CPU executes and the CPU is idle while it fetches.

The 8086 overlaps these two phases:

• While the EU executes the current instruction, the BIU prefetches the next instructions from memory and stores them in the 6-byte queue.
• When the EU finishes, the next instruction is usually already waiting in the queue, so it can begin immediately without a separate fetch delay.
• The BIU refills the queue whenever two or more bytes are empty (the queue is byte-organized, refilled when at least 2 bytes are free).

How Queuing Improves Performance

• Reduces idle bus time – fetch and execute happen in parallel instead of one after another.
• Hides memory-access latency – the EU rarely waits for an instruction fetch.
• Increases throughput – effective instruction rate rises because the fetch time of the next instruction is overlapped with execution of the current one.

Limitation: On a branch/jump or CALL/RET, the prefetched bytes become invalid; the queue is flushed and refilled from the new address, temporarily losing the pipelining benefit.

Diagram (described): Memory and the system bus connect to the BIU (segment registers, IP, 6-byte queue, bus control). The BIU connects internally to the EU (ALU, flags, GP registers, decoder, timing). Instructions flow Memory → BIU queue → EU.

8259 Programmable Interrupt Controller (PIC)

The 8259 is a programmable LSI device that manages hardware interrupts for the 8086/8088. A single 8086 has only one maskable interrupt input (INTR), so the 8259 expands and prioritizes up to 8 interrupt sources (and up to 64 when cascaded), relieving the CPU of polling.

Features

• Handles 8 prioritized interrupt levels (IR0–IR7) per chip.
• Cascadable: one master + up to 8 slaves manage up to 64 interrupts.
• Programmable priority modes: fixed priority, automatic rotation, specific rotation.
• Maskable individual interrupts (via the IMR).
• Selectable edge- or level-triggered inputs.
• Programmable interrupt vector/type number for each input.

Internal Blocks

• IRR (Interrupt Request Register): stores incoming pending requests on IR0–IR7.
• ISR (In-Service Register): marks the interrupt level currently being serviced.
• IMR (Interrupt Mask Register): selectively disables (masks) individual inputs.
• Priority Resolver: decides the highest-priority pending request.
• Control logic, data-bus buffer, read/write logic, cascade buffer.

How It Manages Multiple Interrupts

1. A device raises a request on an IRx line → the corresponding IRR bit is set.
2. The Priority Resolver selects the highest-priority unmasked request and the 8259 asserts INT to the CPU.
3. The CPU responds with the first INTA pulse; the 8259 sets the matching ISR bit and clears the IRR bit.
4. On the second INTA, the 8259 places the interrupt type (vector) number on the data bus; the CPU multiplies it by 4 to index the Interrupt Vector Table and jumps to the ISR.
5. At the end of the service routine, an EOI (End Of Interrupt) command clears the ISR bit so lower-priority interrupts can be serviced.

Programming

The 8259 is set up with ICWs (Initialization Command Words ICW1–ICW4) for triggering mode, cascading, and vector base, and controlled at run time with OCWs (Operation Command Words OCW1–OCW3) for masking, EOI, and priority rotation.

Stack and Subroutine in the Microprocessor

Stack

A stack is a reserved region of read/write memory used as a LIFO (Last-In, First-Out) data structure for temporary storage of return addresses, register contents, and parameters. In the 8086 the stack lies in the stack segment; its top is addressed by SS (segment) and SP (offset). The 8086 stack grows downward (toward lower addresses) and is accessed in word (2-byte) units.

Stack Pointer (SP)

The Stack Pointer is a 16-bit register that always points to the top of the stack. Its physical address is $(\text{SS} \times 16) + \text{SP}$.

• On a push, SP is decremented by 2 before the data is stored.
• On a pop, the data is read and SP is incremented by 2. Thus SP automatically tracks the current top so the program need not manage it manually.

Subroutine

A subroutine (procedure) is a reusable block of code that performs a specific task and is invoked from one or more places by a CALL instruction, returning to the caller with RET. Subroutines reduce code duplication and improve modularity.

Execution of CALL

When a CALL executes:

1. The address of the next instruction (the return address) is pushed onto the stack: SP is decremented and IP (and CS for a far call) is stored.
2. IP (and CS for far call) is loaded with the subroutine's address, transferring control.

NEAR CALL:  SP ← SP − 2 ; [SP] ← IP ; IP ← target
FAR  CALL:  SP ← SP − 2 ; [SP] ← CS
            SP ← SP − 2 ; [SP] ← IP ; CS:IP ← target

Execution of RET

When RET executes at the end of the subroutine:

1. The saved return address is popped from the stack back into IP (and CS for a far return).
2. SP is incremented accordingly, and execution resumes at the instruction following the original CALL.

NEAR RET:  IP ← [SP] ; SP ← SP + 2
FAR  RET:  IP ← [SP] ; SP ← SP + 2 ; CS ← [SP] ; SP ← SP + 2

Because the stack is LIFO, nested and recursive subroutine calls return correctly: the most recently saved return address is the first one restored.

An Interrupt Service Routine (ISR), also called an interrupt handler, is a special subroutine that the processor automatically executes in response to an interrupt request. When an interrupt occurs, the CPU saves the current flags and return address (CS:IP) on the stack, obtains the ISR's address from the Interrupt Vector Table (using the interrupt type number $\times 4$), and jumps to the ISR. The ISR performs the action required by the interrupting device and ends with an IRET instruction, which restores the flags and return address so the interrupted program resumes exactly where it left off.

Function of the 8259 PIC

The 8259 Programmable Interrupt Controller manages hardware interrupts for the 8086, which itself has only one INTR line. Its functions are:

• Expansion: accepts up to 8 interrupt inputs (IR0–IR7) per chip, expandable to 64 by cascading.
• Prioritization: the built-in priority resolver decides which of several simultaneous requests is serviced first.
• Masking: the IMR lets individual interrupts be selectively enabled/disabled.
• Vectoring: on the CPU's INTA pulses, it supplies the interrupt type number, so the CPU can locate the correct ISR via the Interrupt Vector Table.
• Tracking & EOI: it records the interrupt being serviced in the ISR register and clears it on receiving an End-Of-Interrupt command.

In short, the 8259 relieves the CPU from polling by accepting, prioritizing, masking, and vectoring multiple interrupt sources.

Hardware vs. Software Interrupt

Summary: A hardware interrupt comes from outside the CPU through its interrupt pins and arrives asynchronously, whereas a software interrupt is triggered intentionally by an INT instruction in the running program (typically to invoke system/BIOS services).

Logical Instructions of the 8086

These instructions perform bitwise Boolean operations and update the flags (and clear CF and OF in most cases):

• AND – bitwise AND of destination and source; used to mask (clear) selected bits. e.g. AND AL, 0FH
• OR – bitwise OR; used to set selected bits. e.g. OR AL, 80H
• XOR – bitwise exclusive-OR; used to toggle/complement bits or clear a register (XOR AX, AX).
• NOT – ones-complement; inverts every bit of the operand (does not affect flags).
• TEST – performs AND but only sets the flags, discarding the result; used to test bits non-destructively.
• SHL/SAL, SHR, SAR – logical/arithmetic shift left/right.
• ROL, ROR, RCL, RCR – rotate left/right, optionally through the carry flag.

The core bitwise-logic group is AND, OR, XOR, NOT, TEST, often listed together with the shift and rotate instructions.

Role of the Segment Override Prefix

The segment override prefix is a one-byte code placed before an instruction that forces the processor to use a segment register other than the default one when computing the effective memory address.

• By default the 8086 pairs each access with a specific segment: data accesses use DS, stack accesses (involving BP or SP) use SS, instruction fetch uses CS, and string destinations use ES.
• The override prefix (CS:, DS:, ES:, SS:) overrides this default for that single instruction.

Example:

MOV AL, [BX]        ; default → DS:[BX]
MOV AL, ES:[BX]     ; override → ES:[BX]

Here ES: tells the CPU to use the ES segment instead of the default DS to compute the physical address $(\text{ES} \times 16) + \text{BX}$.

Purpose: it gives flexible access to data lying in different segments without permanently changing the segment registers, which is essential in the 8086's segmented memory model. (Note: it cannot override the CS used for instruction fetch or the SS used by stack PUSH/POP.)

Latency and Access Time

Access Time: the time taken between the moment a memory device receives a valid address (and a read/control signal) and the moment the requested data becomes available at its output. It measures how quickly a single requested data item can be obtained, e.g. a memory chip's access time might be 60 ns.

Latency: the total delay between issuing a request (e.g. for a block of data) and the start of the actual data transfer—i.e. the time spent before useful data begins to arrive. In memory systems latency includes the access time plus any additional overhead such as bus arbitration, addressing, and command setup; in rotating storage it includes seek and rotational delay.

Relationship: access time is essentially the device-level component of the broader latency seen by the processor. Lower values of both mean a faster, more responsive memory system.

PUSH and POP Instructions

Both operate on the stack (segment SS, top pointed to by SP) in word (2-byte) units; the 8086 stack grows downward.

PUSH source

Stores a 16-bit operand onto the top of the stack.

SP ← SP − 2
[SP] ← source        ; store the word at the new top

The high byte goes to the higher address and the low byte to the lower address. Example: PUSH AX saves AX so it can be restored later.

POP destination

Retrieves the word from the top of the stack into the destination.

destination ← [SP]   ; read the word at the current top
SP ← SP + 2

Example: POP BX loads the top-of-stack word into BX and frees the slot.

Key Points

• They are complementary: data pushed last is popped first (LIFO).
• Used to save/restore registers, pass parameters, and preserve state during subroutine calls and interrupts.
• Neither instruction affects the flags (except PUSHF/POPF, which save/restore the flag register).
• The operand must be a 16-bit register or memory word (CS cannot be a POP destination).

Function of the TEST Signal (TEST pin)

The TEST input is an active-low control pin of the 8086 used together with the WAIT instruction for synchronization with an external device (typically a coprocessor such as the 8087).

• When the CPU executes the WAIT instruction, it examines the TEST pin.
• If TEST is HIGH (inactive), the processor enters an idle/wait state and keeps checking the pin every few clock cycles.
• When TEST goes LOW (active), the CPU exits the wait state and continues with the next instruction.

This lets the 8086 pause until an external processor signals it is ready, providing handshaking between the CPU and a coprocessor or other slow device. (Note: this hardware TEST pin is different from the TEST logical instruction.)

String Instructions in the 8086

String instructions operate on blocks (strings) of bytes or words stored in memory, processing one element at a time and automatically updating the index registers so that long data blocks can be handled efficiently.

Registers and Conventions

• SI points to the source string (in DS), DI points to the destination string (in ES).
• After each operation SI/DI are auto-incremented (if the Direction Flag DF = 0) or auto-decremented (if DF = 1, set by STD/cleared by CLD), by 1 for bytes or 2 for words.

Main String Instructions

• MOVS / MOVSB / MOVSW – move (copy) a byte/word from DS:SI to ES:DI.
• CMPS / CMPSB / CMPSW – compare a source element with a destination element and set flags.
• SCAS / SCASB / SCASW – scan (compare) the AL/AX accumulator against ES:DI.
• LODS / LODSB / LODSW – load a byte/word from DS:SI into AL/AX.
• STOS / STOSB / STOSW – store AL/AX into ES:DI.

REP Prefix

The REP / REPE / REPZ / REPNE / REPNZ prefixes repeat a string instruction using CX as a counter (decremented each iteration), optionally testing the Zero Flag. This allows entire strings to be moved, compared, or filled with a single instruction.

Example:

CLD                 ; auto-increment
MOV CX, 100
REP MOVSB           ; copy 100 bytes from DS:SI to ES:DI