BSc CSIT (TU) Science Microprocessor (BSc CSIT, CSC162) Question Paper 2074 Nepal

Internal Architecture of the Intel 8085

The Intel 8085 is an 8-bit microprocessor with a 16-bit address bus and an 8-bit data bus. Its internal architecture is organized around the following functional blocks.

Block Diagram (described)

The ALU, accumulator and flag register sit on the left, connected to an 8-bit internal data bus. The register array (B, C, D, E, H, L, SP, PC and temporary registers) connects to the same bus. The timing & control unit and instruction decoder sit at the top, driving control signals, while the interrupt control and serial I/O control blocks sit on the right. The address buffer and address/data buffer drive the external A8-A15 and AD0-AD7 lines.

Functional Blocks

1. Arithmetic and Logic Unit (ALU) Performs arithmetic ($+,-$) and logical (AND, OR, XOR, complement, shift/rotate) operations on 8-bit data. Operands come from the accumulator and a temporary register; the result returns to the accumulator and sets the flags.

2. Accumulator (A) An 8-bit register that holds one operand before an operation and stores the result after it. Most arithmetic/logic and I/O operations use the accumulator.

3. Flag Register A 5-bit status register (S, Z, AC, P, CY) that records the result condition of ALU operations and is used for conditional branching.

4. General-Purpose Registers (B, C, D, E, H, L) Six 8-bit registers that can be used singly or paired as 16-bit registers BC, DE, HL for holding data and addresses (HL is also a memory pointer).

5. Program Counter (PC) A 16-bit register holding the address of the next instruction to be fetched; it is automatically incremented after each fetch.

6. Stack Pointer (SP) A 16-bit register that points to the top of the stack in memory, used during PUSH/POP and subroutine CALL/RETURN.

7. Instruction Register and Decoder The fetched opcode is latched in the instruction register and decoded to generate the control sequence for execution.

8. Timing and Control Unit Generates control and status signals ($\overline{RD}, \overline{WR}, ALE, IO/\overline{M}, S_0, S_1$) and synchronizes all operations with the system clock (CLK from a crystal via X1, X2).

9. Interrupt Control Handles the five hardware interrupts (TRAP, RST 7.5, RST 6.5, RST 5.5, INTR) and the acknowledge signal INTA.

10. Serial I/O Control Provides serial communication through SID (Serial Input Data) and SOD (Serial Output Data) lines, used by RIM/SIM instructions.

11. Address Buffer and Address/Data Buffer The high-order address (A8-A15) is sent through the address buffer; the lower 8 lines (AD0-AD7) are multiplexed for both the low-order address and data, demultiplexed externally with the ALE signal.

Addressing Modes of the 8086

An addressing mode specifies how the operand of an instruction is located. The 8086 supports the following modes.

1. Register Addressing — operand is in a register.

MOV AX, BX      ; copy contents of BX into AX

2. Immediate Addressing — operand is a constant given in the instruction.

MOV AL, 25H     ; load 25H directly into AL

3. Direct Addressing — the effective address (offset) of the operand is given directly.

MOV AX, [5000H] ; load word at offset 5000H in data segment

4. Register Indirect Addressing — the offset is held in a base/index register (BX, SI, DI).

MOV AX, [BX]    ; load word from address pointed to by BX

5. Based Addressing — effective address = base register (BX/BP) + displacement.

MOV AX, [BX+4]  ; offset = BX + 4

6. Indexed Addressing — effective address = index register (SI/DI) + displacement.

MOV AX, [SI+2]  ; offset = SI + 2

7. Based-Indexed Addressing — effective address = base + index register.

MOV AX, [BX+SI] ; offset = BX + SI

8. Based-Indexed with Displacement — effective address = base + index + displacement.

MOV AX, [BX+SI+8]

9. String Addressing — implicitly uses SI (source) and DI (destination) with auto-increment/decrement.

MOVSB           ; move byte from DS:SI to ES:DI

In each memory case the physical address is computed as $PA = (\text{segment} \times 16) + \text{offset}$.

Memory and I/O Interfacing

Interfacing is the technique of connecting memory chips and I/O devices to the microprocessor's address, data and control buses so that they respond only when selected. The address bus selects a location, the data bus transfers the byte/word, and the control signals ($\overline{RD}, \overline{WR}, IO/\overline{M}$ in 8085) decide direction and target. A decoder (e.g. 3-to-8 line) generates chip-select ($\overline{CS}$) signals from the high-order address lines so that each chip occupies a unique address range.

There are two schemes to address I/O ports.

Memory-Mapped I/O

I/O ports are treated like memory locations and assigned addresses from the common memory address space. Data transfer uses ordinary memory instructions (e.g. LDA, STA, MOV M).

Advantages: full 16-bit address range available to ports; all memory-reference instructions and addressing modes can be used; simpler control logic ($IO/\overline{M}$ not needed).

Disadvantages: port addresses consume part of the memory space, reducing memory available; address decoding needs all 16 lines, so decoding hardware is larger.

Isolated (I/O-Mapped) I/O

I/O ports have a separate address space from memory; transfers use dedicated IN/OUT instructions, and the processor distinguishes them with the $IO/\overline{M}$ line.

Advantages: no memory space is lost to ports; only 8 address lines (256 ports) are decoded, so decoding is simpler; clear separation of memory and I/O.

Disadvantages: only IN/OUT instructions (and only the accumulator) can be used, so addressing is limited; an extra control signal is required to differentiate memory from I/O.

A microprocessor is a single-chip CPU containing the ALU, registers and control unit; it requires external memory (RAM/ROM) and I/O chips to form a working computer (e.g. Intel 8085, 8086).

A microcontroller is a single chip that integrates a CPU together with on-chip memory (RAM and ROM), I/O ports, timers and other peripherals, forming a complete computer for embedded control (e.g. Intel 8051).

The Arithmetic and Logic Unit (ALU) is the part of the microprocessor that performs all data-processing operations. Its functions are:

• Arithmetic operations: addition, subtraction, increment, decrement and comparison of binary numbers.
• Logical operations: AND, OR, XOR, NOT (complement).
• Shift and rotate operations on data bits.

It takes operands from the accumulator and a temporary register, performs the selected operation, returns the result to the accumulator, and updates the flag register (S, Z, AC, P, CY) to reflect the nature of the result.

Flag Register of the 8085

The flag register is an 8-bit register in which five bits are used as status flags. They are set or reset automatically after arithmetic and logical operations to indicate the result condition, and are tested by conditional jump/call/return instructions.

Bits D1, D3 and D5 are undefined (not used). Together with the accumulator, the flag register forms the Program Status Word (PSW).

An instruction cycle is the total time (and sequence of operations) the microprocessor takes to fetch, decode and execute one complete instruction.

It consists of one or more machine cycles, and each machine cycle in turn is made up of several T-states (clock periods). In general:

The fetch part reads the opcode from memory; the execute part decodes it and carries out the required operation. A simple instruction may need just one machine cycle, while a complex one may need several.

The 8086 has four 16-bit segment registers, each pointing to the base of a 64 KB segment:

1. CS (Code Segment) — holds the base address of the segment containing program instructions.
2. DS (Data Segment) — holds the base address of the segment containing program data.
3. SS (Stack Segment) — holds the base address of the stack segment.
4. ES (Extra Segment) — an additional data segment, used mainly in string operations.

The physical address is formed as $PA = (\text{segment register} \times 16) + \text{offset}$.

A machine cycle is the time required by the microprocessor to perform one operation of accessing memory or an I/O device — for example, an opcode fetch, a memory read, a memory write, an I/O read or an I/O write.

Each machine cycle is made up of a number of T-states (clock cycles), typically 3 to 6 in the 8085. One instruction cycle consists of one or more machine cycles:

For example, the opcode-fetch machine cycle of the 8085 takes 4 T-states (or 6 for some instructions).

RISC vs CISC

The stack pointer (SP) is a special 16-bit register that always points to the top of the stack — a LIFO (Last-In-First-Out) area of read/write memory.

Its uses are:

• During PUSH, the data is stored at the stack location and SP is decremented; during POP, data is read back and SP is incremented.
• During a CALL instruction, the return address (contents of the PC) is automatically saved on the stack using SP; on RET it is restored.
• It is used to save and restore registers and to handle interrupts and nested subroutines.

Thus the stack pointer keeps track of where the next item will be stored or retrieved in the stack.

An addressing mode is the method by which the location of an operand is specified in an instruction — that is, how the processor determines where to get the data to be operated on or where to store the result.

It may specify the operand as an immediate constant, the contents of a register, or a memory location whose address is formed directly or indirectly (through registers and displacements). Addressing modes make programming flexible and efficient. Common examples include immediate, register, direct, register-indirect and indexed addressing.