BSc CSIT (TU) Science Microprocessor (BSc CSIT, CSC162) Question Paper 2075 Nepal

Architecture of the 8086 Microprocessor

The 8086 is a 16-bit microprocessor that internally divides its work between two independent functional units that work in parallel (pipelining): the Bus Interface Unit (BIU) and the Execution Unit (EU).

Block Diagram (described)

• BIU (top): contains the four segment registers (CS, DS, SS, ES), the Instruction Pointer (IP), the address generation/adder unit, and a 6-byte instruction queue. It connects to the system bus.
• EU (bottom): contains the ALU, the general-purpose registers (AX, BX, CX, DX), the pointer/index registers (SP, BP, SI, DI), the flag register, and the control/timing circuitry.
• The two units communicate through an internal bus; the BIU feeds prefetched instruction bytes into the queue, and the EU pulls them out for decoding/execution.

Bus Interface Unit (BIU)

The BIU handles all transfers between the CPU and memory/I/O.

• Generates the 20-bit physical address by shifting the segment register left by 4 bits and adding the offset: $\text{Physical Address} = (\text{Segment} \times 16) + \text{Offset}$.
• Fetches instructions in advance and stores them in the 6-byte instruction queue (instruction prefetching / pipelining).
• Performs read/write of data operands from memory and I/O ports.
• Holds CS, DS, SS, ES segment registers and IP.

Execution Unit (EU)

The EU executes the instructions supplied by the BIU.

• Decodes and executes instructions taken from the queue.
• Performs all arithmetic and logical operations through the 16-bit ALU.
• Holds general-purpose registers (AX, BX, CX, DX), index/pointer registers, and the flag register.
• Tells the BIU where to fetch the next data or instruction (it has no direct connection to the system bus).

BIU vs EU

Parallelism: While the EU executes one instruction, the BIU prefetches the next ones into the queue, reducing the time the CPU waits on memory and improving throughput.

Interrupts in the 8085

An interrupt is a signal (from hardware or software) that temporarily halts the normal execution of the main program so the CPU can service a higher-priority event. The CPU saves the current state (pushes the program counter on the stack), executes an Interrupt Service Routine (ISR), and then resumes the interrupted program.

Hardware Interrupts of 8085

The 8085 has five hardware interrupt pins:

• TRAP cannot be disabled by software; it is used for critical events such as power failure.
• RST 7.5, 6.5, 5.5 are vectored and can be masked/unmasked using the SIM instruction; their status is read using RIM.
• INTR is non-vectored: the interrupting device supplies the instruction (usually an RST or CALL) during the interrupt-acknowledge (INTA) cycle.

Software Interrupts of 8085

These are RST n instructions ($n = 0$ to $7$) written inside the program. Each calls a fixed vector location $= n \times 8$:

• RST 0 → 0000H, RST 1 → 0008H, RST 2 → 0010H, RST 3 → 0018H, RST 4 → 0020H, RST 5 → 0028H, RST 6 → 0030H, RST 7 → 0038H.

Priority Order (highest to lowest)

When two interrupts occur simultaneously, the one higher in this order is serviced first.

8086 Pin Diagram and Signals in Minimum Mode

The 8086 is a 40-pin dual-in-line package operating on +5 V. The pin MN/$\overline{MX}$ selects the mode: tied to +5 V (logic 1) gives minimum mode (single-processor system).

Multiplexed and Common Signals

• AD0–AD15: Time-multiplexed address/data bus. They carry the lower 16 address bits when ALE = 1 and data during the rest of the cycle.
• A16/S3 – A19/S6: Multiplexed upper address bits / status lines.
• $\overline{BHE}$/S7: Bus High Enable, used to access the upper byte of the data bus.
• CLK, RESET, READY: Clock, reset, and wait-state synchronization.
• NMI, INTR: Interrupt inputs; $\overline{INTA}$ is the acknowledge output.
• TEST, MN/$\overline{MX}$, Vcc, GND.

Signals specific to Minimum Mode (generated by the 8086 itself)

Operation summary

In minimum mode the 8086 directly produces the control signals (ALE, RD, WR, M/IO, DEN, DT/R), so no external bus controller (8288) is needed. ALE strobes the lower address into latches to demultiplex the AD lines, then the same lines carry data controlled by RD/WR.

The word length of the 8086 is 16 bits. It has a 16-bit ALU and 16-bit internal data registers, so it processes data 16 bits (one word) at a time. (Its external data bus is also 16 bits wide, while its address bus is 20 bits, addressing 1 MB of memory.)

• Opcode (Operation Code): The part of a machine/assembly instruction that specifies which operation the CPU must perform (e.g., ADD, MOV, SUB).
• Operand: The part of the instruction that specifies the data or the address/register on which the operation is performed.

Example: In MOV AX, BX → MOV is the opcode, while AX and BX are the operands.

• Maskable interrupt: An interrupt that the programmer can enable or disable (mask) through software instructions (e.g., EI/DI or SIM in 8085). The CPU may ignore it if interrupts are disabled. Examples: INTR, RST 7.5/6.5/5.5.
• Non-maskable interrupt (NMI): An interrupt that cannot be disabled by software; the CPU must always service it. It is reserved for critical/emergency conditions such as power failure. Example: TRAP in the 8085, NMI in the 8086.

Key difference: Maskable interrupts can be turned off under program control; non-maskable interrupts always have the highest priority and are always recognized.

The Instruction Pointer (IP) is a 16-bit register that holds the offset address of the next instruction to be fetched within the current code segment. Together with the CS (Code Segment) register it forms the full physical address:

After each instruction is fetched, the BIU automatically increments the IP to point to the next instruction. The IP cannot be directly modified by the programmer; it is changed by control-transfer instructions such as JMP, CALL, RET, and interrupts. (It is analogous to the Program Counter in the 8085.)

Immediate Addressing Mode

In immediate addressing mode, the operand (the actual data) is specified directly within the instruction itself, immediately after the opcode. No memory or register access is needed to obtain the operand, so it executes quickly. It is used to load constants into registers or memory.

Examples (8086):

MOV AX, 1234H   ; load immediate value 1234H into AX
ADD BX, 05H     ; add immediate constant 05H to BX
MOV CL, 0AH     ; load 0AH into CL

Here 1234H, 05H, and 0AH are immediate operands stored as part of the instruction code. Note that the destination cannot be a segment register in immediate mode.

Role of the ALE Signal in 8085

ALE (Address Latch Enable) is an output signal of the 8085 used to demultiplex the lower-order address/data bus AD0–AD7.

• The lines AD0–AD7 are time-multiplexed: in the first T-state (T1) of a machine cycle they carry the lower byte of the address, and later they carry data.
• The 8085 issues a positive (high) pulse on ALE during T1. This pulse is used to latch the lower address byte into an external latch (e.g., 8212 / 74LS373).
• After ALE goes low, the same AD0–AD7 lines are free to be used as the data bus, while the latched address remains stable on the latch outputs.

Thus ALE separates the address from the data on the shared bus, allowing the 8085 to use one set of pins for both purposes.

• Clock speed (clock frequency): The rate at which the processor's internal clock generates pulses, measured in Hertz (MHz/GHz). It defines the basic timing of operations; one clock cycle time $T = 1/f$. A higher clock speed generally means instructions execute faster.
• Throughput: The number of instructions (or amount of work/data) the processor completes per unit time, e.g., instructions per second (MIPS) or bytes per second. It reflects actual processing performance and depends on clock speed, pipelining, instruction complexity, and memory access.

Relation: A high clock speed raises the potential speed, but real throughput also depends on architecture (pipelining, parallelism, stalls).

A control bus is a group of signal lines that carries control and timing signals between the microprocessor and the other components (memory and I/O devices). Unlike the address and data buses, the control bus is not a single multi-bit value but a set of individual control lines.

Typical control signals include:

• $\overline{\text{RD}}$ (Read) and $\overline{\text{WR}}$ (Write) — direction of data transfer.
• $\text{M/}\overline{\text{IO}}$ — selects memory or I/O operation.
• ALE, READY, RESET, CLK, INTR/INTA, HOLD/HLDA — timing, synchronization, interrupt and DMA control.

It coordinates when and what type of operation occurs, so the CPU and devices act in proper sequence.

Memory-Mapped I/O vs I/O-Mapped I/O

Summary: In memory-mapped I/O, ports are treated like memory locations and accessed by ordinary memory instructions; in I/O-mapped I/O, ports occupy a distinct address space accessed only by dedicated IN/OUT instructions distinguished by the $\text{M/}\overline{\text{IO}}$ (or IO/M) control line.