BSc CSIT (TU) Science Microprocessor (BSc CSIT, CSC162) Question Paper 2077 Nepal

Register Organization of the 8086 Microprocessor

The 8086 has fourteen 16-bit registers grouped into four categories.

1. General Purpose Registers (Data Registers)

Four 16-bit registers, each split into a high and low byte so they can be used as 8-bit registers too:

2. Segment Registers (16-bit)

They hold the base (paragraph) addresses of the four active segments:

• CS – Code Segment (instructions, used with IP)
• DS – Data Segment (data variables)
• SS – Stack Segment (stack, used with SP/BP)
• ES – Extra Segment (string destination, used with DI)

3. Pointer and Index Registers (16-bit)

Used to hold offsets within a segment:

• SP – Stack Pointer → top of stack (with SS)
• BP – Base Pointer → base of stack frame (with SS)
• SI – Source Index → source offset in string operations (with DS)
• DI – Destination Index → destination offset (with ES)
• IP – Instruction Pointer → offset of the next instruction (with CS); cannot be accessed directly.

4. Flag Register (16-bit, FLAGS)

Nine active flags out of 16 bits.

Status (conditional) flags — set by the result of an operation: CF (Carry), PF (Parity), AF (Auxiliary carry), ZF (Zero), SF (Sign), OF (Overflow).

Control flags — set by the programmer to control processor behaviour: TF (Trap, single-step), IF (Interrupt enable), DF (Direction for string ops).

Bit layout: | - | - | - | - | OF | DF | IF | TF | SF | ZF | - | AF | - | PF | - | CF |

Memory Segmentation in the 8086

The 8086 has a 20-bit address bus, so it can address $2^{20} = 1\,\text{MB}$ of memory, but all its registers are only 16-bit (addressing $2^{16} = 64\,\text{KB}$). Segmentation is the technique of dividing the 1 MB memory into logical segments of up to 64 KB, each pointed to by a 16-bit segment register, so that a 16-bit machine can reach a 20-bit address space.

Physical Address Generation

A memory location is specified by a segment (in a segment register) and an offset (in a pointer/index register or from the instruction). The Bus Interface Unit forms the physical address by:

Multiplying by 10H is the same as shifting the segment value left by 4 bits (appending one hex zero), giving the 20-bit base of the segment, to which the 16-bit offset is added.

Example: CS = 1000H, IP = 2000H

Why Segmentation Is Used

• Allows a 16-bit processor to access 1 MB of memory.
• Programs (code, data, stack) are relocatable — only the segment register need change to move a program in memory.
• Separates code, data and stack into independent regions, improving organisation and protection.
• Permits more efficient use of memory for multiprogramming.

8255 Programmable Peripheral Interface (PPI)

The 8255 is a general-purpose programmable parallel I/O device used to interface peripherals with the microprocessor. It provides 24 I/O lines arranged as three 8-bit ports, and these can be programmed in several modes by writing a control word.

Block Diagram (described)

The internal structure consists of:

• Data bus buffer – tri-state 8-bit bidirectional buffer that connects the 8255 to the system data bus (D0–D7).
• Read/Write control logic – takes RD̄, WR̄, RESET, CS̄ and address lines A0, A1 to select the addressed register and control data flow.
• Group A control – manages Port A (PA0–PA7) and the upper half of Port C (PC4–PC7).
• Group B control – manages Port B (PB0–PB7) and the lower half of Port C (PC0–PC3).

A1 A0: 00 → Port A, 01 → Port B, 10 → Port C, 11 → Control register.

Modes of Operation

Bit Set/Reset (BSR) mode – used to set or reset individual bits of Port C (control word MSB = 0).

I/O mode (control word MSB = 1):

• Mode 0 – Simple I/O: Ports A, B and the two halves of C act as independent simple input or output ports; no handshaking.
• Mode 1 – Handshake I/O: Ports A and B work as input or output with handshaking signals; Port C lines supply the handshake control/status signals (STB̄, IBF, INTR, etc.).
• Mode 2 – Bidirectional I/O: Only Port A can transfer data in both directions with handshaking; Port C provides the control signals.

Control Word Format (I/O mode, D7 = 1)

Example: Control word 98H = 1001 1000 → Mode 0, Port A input, Port C-upper input, Port B output, Port C-lower output.

Pipelining is the technique of overlapping the execution of instructions by fetching the next instruction(s) while the current one is being decoded/executed, instead of doing fetch and execute strictly one after another. In the 8086 the Bus Interface Unit (BIU) prefetches up to 6 bytes of instruction code into a queue while the Execution Unit (EU) executes the current instruction. This keeps the EU busy, reduces idle bus time and increases overall throughput/speed of the processor.

Physical Address $= (\text{CS} \times 10\text{H}) + \text{IP}$

The physical address is 12000H.

The READY signal is an input to the 8086 used to synchronise the processor with slow memory or I/O devices. When an addressed device cannot supply or accept data within the normal bus cycle, it pulls READY low, forcing the 8086 to insert wait states (Tw) between T3 and T4 of the machine cycle. The processor keeps inserting wait states until READY goes high, indicating the device is ready, after which the cycle completes. Thus READY prevents data loss when interfacing slow peripherals.

Any four arithmetic instructions of the 8086:

1. ADD – adds source to destination (e.g. ADD AX, BX).
2. SUB – subtracts source from destination (e.g. SUB AX, BX).
3. MUL – unsigned multiplication (e.g. MUL BL).
4. DIV – unsigned division (e.g. DIV BL).

(Other valid examples: ADC, SBB, INC, DEC, IMUL, IDIV, CMP, NEG.)

Near vs Far Procedures

In short, a near procedure is called within one 64 KB segment and saves only the return offset, whereas a far procedure is called across segments and saves both the segment and the offset of the return address.

The 8255 PPI (Programmable Peripheral Interface) is a general-purpose programmable parallel I/O chip used to connect peripheral devices (such as keyboards, displays, printers, ADCs) to the microprocessor. It provides 24 programmable I/O lines organised as three 8-bit ports — Port A, Port B and Port C — controlled in two groups (A and B). By writing a control word to its control register, the programmer configures each port as input or output and selects the operating mode (Mode 0 simple I/O, Mode 1 handshake I/O, Mode 2 bidirectional, or BSR mode for individual Port-C bits). It thus offers flexible, software-configurable parallel data transfer between the CPU and peripherals.

In register addressing mode, the operand to be processed is held inside a CPU register rather than in memory; both source and destination can be registers. Since no memory access is needed, this is the fastest addressing mode.

Examples:

• MOV AX, BX → copies the contents of register BX into register AX.
• ADD CX, DX → adds the contents of DX to CX.
• MOV AL, BL → copies BL into AL (8-bit).

Here the data resides in registers (AX, BX, CX, etc.), so no effective address calculation or memory cycle is required.

The flag register of the 8086 is 16 bits (2 bytes) wide. Out of these 16 bits, 9 flags are used — 6 status/conditional flags (CF, PF, AF, ZF, SF, OF) and 3 control flags (TF, IF, DF) — and the remaining bits are undefined/reserved.

A vectored interrupt is an interrupt for which the address of its service routine (the interrupt vector) is predefined/fixed and supplied automatically, so the processor knows exactly where to branch without polling devices to find the source. In the 8086, each interrupt has a type number (0–255) that the CPU multiplies by 4 to index into the Interrupt Vector Table (IVT) in the first 1 KB of memory; that table entry gives the CS:IP of the corresponding Interrupt Service Routine. Thus control is transferred directly to the correct ISR via its vector, making the response fast and unambiguous.