BSc CSIT (TU) Science Microprocessor (BSc CSIT, CSC162) Question Paper 2079 Nepal

Minimum Mode vs Maximum Mode of 8086

The operating mode of the 8086 is selected by the MN/MX̄ pin (pin 33).

• MN/MX̄ = 1 (logic high → +5 V): Minimum mode. The 8086 works as a single processor system and generates all control signals itself.
• MN/MX̄ = 0 (logic low → grounded): Maximum mode. The 8086 is used in a multiprocessor system (e.g. with the 8087 NDP or 8089 IOP), and the 8288 Bus Controller generates the control signals.

Minimum Mode

In minimum mode, the processor directly produces the control signals ALE, DEN, DT/R̄, M/IŌ, WR̄, RD̄, INTĀ, HOLD, HLDA.

           +5V
            |
  MN/MX(33)-+
  8086 ---> ALE, DT/R, DEN, M/IO, RD, WR, INTA  (direct control signals)
        |--> AD0-AD15 (multiplexed addr/data) --> 8282 latches / 8286 transceivers
        |--> HOLD / HLDA  (DMA handshake)

Diagram (described): the single 8086 drives 8282/8283 address latches (strobed by ALE) and 8286/8287 data transceivers (enabled by DEN, direction by DT/R̄); a clock comes from the 8284.

Maximum Mode

In maximum mode the pins 24–31 are redefined to output status signals S̄0, S̄1, S̄2, QS0, QS1, LOCK̄, RQ̄/GT̄0, RQ̄/GT̄1. The three status lines S̄0–S̄2 are decoded by the external 8288 Bus Controller, which generates the system bus commands.

          GND
           |
  MN/MX(33)-+
  8086 ---> S0,S1,S2 ----> 8288 Bus Controller ----> MRDC, MWTC, IORC, IOWC, ALE, DEN, DT/R
        |--> QS0,QS1 (queue status) --> 8087 / coprocessor
        |--> RQ/GT0, RQ/GT1 (request/grant for coprocessors)
        |--> LOCK (bus lock for atomic ops)

Diagram (described): the 8086 feeds S̄0–S̄2 to the 8288, which issues separate memory and I/O read/write commands; RQ̄/GT̄ lines handle bus arbitration with coprocessors.

Comparison Table

Conclusion: Minimum mode suits small, single-CPU systems and is simpler/cheaper, whereas maximum mode supports coprocessors and multiprocessing at the cost of the extra 8288 bus controller and arbitration logic.

Direct Memory Access (DMA)

DMA is a data-transfer technique in which data is moved directly between an I/O device and memory without the continuous involvement of the CPU. For high-speed devices (disk, network), programmed I/O is too slow because every byte passes through the CPU; DMA lets a dedicated controller take over the system buses and perform the transfer, while the CPU is freed for other work.

DMA Handshake with the CPU

1. The I/O device asserts DREQ (DMA request) to the controller.
2. The DMA controller asserts HOLD to the CPU.
3. The CPU finishes the current bus cycle, floats (tri-states) its buses, and replies with HLDA (Hold Acknowledge).
4. The DMA controller now owns the buses, asserts DACK to the device, and transfers data between memory and the device.
5. On completion, the controller deasserts HOLD; the CPU regains the buses.

The 8237 DMA Controller

The Intel 8237 is a 4-channel programmable DMA controller. Key features:

• 4 independent channels (0–3), each with its own 16-bit address register and 16-bit count register.
• Transfers up to 64 KB per channel; addresses can auto-increment/decrement.
• Provides DREQ0–3 / DACK0–3 handshake lines per channel.
• Internal registers: Command, Mode, Request, Mask, Status registers, plus base/current address and count registers.
• Priority logic: fixed or rotating priority among the four channels.

Transfer Modes

• Single transfer mode – one byte per HOLD/HLDA cycle (CPU regains bus between bytes).
• Block transfer mode – the whole block is transferred in one acquisition.
• Demand transfer mode – transfers continue as long as DREQ is active.
• Cascade mode – multiple 8237s are chained for more than 4 channels.

Transfer Types

• Read transfer – memory → I/O device.
• Write transfer – I/O device → memory.
• Verify transfer – dummy transfer (no actual data movement) used for testing.

DMA Transfer Process (step by step)

1. The CPU programs the 8237: writes the starting memory address, word count, mode and direction into the selected channel's registers, then unmasks the channel.
2. The I/O device requests service via DREQ.
3. The 8237 issues HRQ → CPU's HOLD; CPU responds with HLDA.
4. The 8237 takes the bus, sends DACK to the device, and drives the memory address.
5. It generates simultaneous memory and I/O read/write strobes so a byte moves directly between memory and device. The address is incremented and the count decremented.
6. Steps repeat until the count reaches zero, at which point the channel asserts the Terminal Count (TC/EOP̄) signal.
7. The 8237 releases HOLD; the CPU resumes normal operation.

Advantages: very high transfer speed and minimal CPU load, ideal for bulk transfers.

Assembly Program: Add Two 16-bit Numbers (8086)

This program adds two 16-bit numbers and stores the 16-bit sum (with the carry, if any, in the next location).

.MODEL SMALL
.DATA
    NUM1   DW  1234H        ; first 16-bit operand
    NUM2   DW  5678H        ; second 16-bit operand
    RESULT DW  ?            ; 16-bit sum stored here
    CARRY  DB  ?            ; carry-out (1 if overflow past 16 bits)
.CODE
START:
    MOV  AX, @DATA          ; initialise data segment
    MOV  DS, AX

    MOV  AX, NUM1           ; AX <- first number
    ADD  AX, NUM2           ; AX <- NUM1 + NUM2, CF set on carry-out
    MOV  RESULT, AX         ; store 16-bit sum

    MOV  BL, 0
    ADC  BL, 0             ; BL <- 0 + CF  (capture the carry bit)
    MOV  CARRY, BL          ; store carry

    MOV  AH, 4CH            ; return to DOS
    INT  21H
END START

Example: 1234H + 5678H = 68ACH, CF = 0, so RESULT = 68ACH, CARRY = 00H.

Use of Registers

• AX (accumulator): holds the first operand and receives the sum; the ADD/ADC arithmetic instructions use it as the default 16-bit accumulator.
• DS: points to the data segment so NUM1, NUM2, RESULT can be accessed.
• BL: temporarily holds and stores the carry bit using ADC.
• AH = 4CH with INT 21H: DOS function to terminate the program.

Use of Flags (FLAGS register)

The ADD instruction updates the status flags according to the result:

Here CF is the important flag: if the 16-bit sum overflows, CF = 1 and ADC propagates it into the carry byte. This is exactly how multi-word (32-bit, 64-bit) additions are chained using ADD for the lowest word and ADC for the higher words.

Minimum vs Maximum Mode (8086):

Minimum mode is simpler and used for small single-CPU systems; maximum mode supports coprocessors/multiprocessing using the extra 8288 controller.

A DMA controller is a programmable hardware device (e.g. the Intel 8237) that manages Direct Memory Access, allowing data to be transferred directly between an I/O device and memory without routing every byte through the CPU.

When an I/O device requests service (DREQ), the controller asks the CPU for the buses via HOLD; the CPU floats its buses and replies with HLDA. The controller then drives the address/data/control buses, sends DACK to the device, and transfers the data block, incrementing the address and decrementing the count until the terminal count (EOP̄) is reached, after which it returns the buses to the CPU.

This offloads bulk transfers from the CPU and gives much higher throughput for fast devices such as disks and network cards.

The LOOP Instruction (8086)

Syntax: LOOP label

The LOOP instruction implements a counter-controlled loop using the CX register as the loop counter. Each time it executes it:

1. Decrements CX by 1 (this does not affect the flags).
2. If CX ≠ 0, it jumps (a short jump, −128 to +127 bytes) to the target label.
3. If CX = 0, it falls through to the next instruction, ending the loop.

So LOOP is equivalent to DEC CX followed by JNZ label, but in a single instruction.

    MOV CX, 5        ; loop will run 5 times
BACK:
    ; ... body ...
    LOOP BACK        ; CX = CX-1; if CX != 0 goto BACK

Variants:

• LOOPE / LOOPZ label – loops while CX ≠ 0 and ZF = 1.
• LOOPNE / LOOPNZ label – loops while CX ≠ 0 and ZF = 0.

Note: if CX = 0 at entry, LOOP decrements it to FFFFH and executes 65536 times, so CX should be initialised to the desired count before the loop.

Both are status flags in the 8086 FLAGS register, set/cleared by the result of arithmetic/logical operations.

Auxiliary Carry Flag (AF)

• AF = 1 when there is a carry-out (or borrow) from bit 3 to bit 4 of the low byte, i.e. a carry across the lower nibble boundary.
• It is not tested directly by conditional jumps; it is used exclusively by the BCD-adjust instructions AAA, AAS, DAA, DAS to correct packed/unpacked BCD arithmetic.
• Example: 0FH + 01H = 10H produces a carry from bit 3 → bit 4, so AF = 1.

Parity Flag (PF)

• PF = 1 when the low-order 8 bits of the result contain an even number of 1s (even parity); PF = 0 for odd parity.
• Used in data-communication / error-checking routines and tested with JP/JPE (jump if parity even) and JNP/JPO (jump if parity odd).
• Example: result low byte 0F0H (11110000) has four 1s → even → PF = 1.

HLDA Signal (Hold Acknowledge)

HLDA is an output signal of the 8086 (used in minimum mode) that the processor asserts in response to a HOLD request.

Working / DMA handshake:

1. A bus master (e.g. a DMA controller) requests the system buses by asserting HOLD (an input to the 8086).
2. The 8086 completes its current bus cycle, then tri-states (floats) its address, data and control buses.
3. It asserts HLDA = 1 to acknowledge that it has released the buses.
4. The requesting device now controls the buses and performs its transfer (e.g. DMA between memory and I/O).
5. When the device deasserts HOLD, the 8086 drives HLDA low and resumes normal operation, regaining control of the buses.

Thus HLDA tells the requesting device that the CPU has surrendered the buses, enabling DMA and other bus-mastering operations. (In maximum mode the equivalent function is handled by the RQ̄/GT̄ request/grant lines.)

CALL vs JMP

Both transfer program control to another location, but CALL is used for subroutines and JMP for unconditional branches.

    CALL DELAY      ; save IP, jump to DELAY; RET comes back here
    ...
DELAY:
    ...
    RET             ; pop saved IP, return to caller

    JMP  NEXT       ; just go to NEXT, no return

Summary: CALL saves the return address so execution can come back with RET; JMP transfers control permanently without saving any return information.

8284 Clock Generator

The Intel 8284A is a clock-generator and driver chip used with the 8086/8088. Its main functions are:

1. Clock generation (CLK): Using an external crystal (across X1, X2) or an external oscillator (EFI input), it divides the crystal frequency by 3 to produce the system clock CLK with the required 33% duty cycle that the 8086 needs. (e.g. a 15 MHz crystal → 5 MHz CLK.)
2. PCLK (Peripheral Clock): Provides a TTL-level peripheral clock at ½ of CLK (50% duty cycle) for peripheral devices.
3. RESET synchronization: Accepts the asynchronous RES̄ input (via an RC power-on circuit) and produces a clean, clock-synchronized RESET signal for the 8086.
4. READY synchronization: Synchronizes the asynchronous ready inputs RDY1/RDY2 (with AEN1̄/AEN2̄ enables) to the CPU clock and outputs a stable READY signal, which is used to insert wait states for slow memory/I/O.
5. OSC output: Provides the buffered crystal oscillator output (3× CLK) for other system uses.

In short, the 8284 supplies a stable, correctly shaped clock and provides synchronized RESET and READY signals required for proper 8086 operation.

Bus Contention

Bus contention is the conflict that occurs when two or more devices attempt to drive the same shared bus (data/address) line at the same time — one trying to output a logic 0 and another a logic 1.

Cause: failure to coordinate which device owns the bus, e.g. overlapping enable signals for buffers/transceivers, or two bus masters (CPU and DMA) active simultaneously.

Effects:

• The bus settles to an indeterminate/invalid logic level, producing erroneous data.
• Large currents can flow between the conflicting drivers, causing excess power dissipation and possible damage to the devices.

Prevention:

• Use tri-state buffers/transceivers (e.g. 8286) and ensure only one device drives the bus at a time via proper enable (DEN, DT/R̄) control.
• Use bus arbitration (HOLD/HLDA or RQ̄/GT̄) so masters take turns.
• Insert dead time between disabling one driver and enabling another.

Proper bus arbitration and timing guarantee that exactly one driver is active, avoiding contention.

Direct Addressing Mode

In direct addressing mode, the effective address (offset) of the operand is given directly in the instruction as a constant displacement. The processor combines this offset with the data segment (DS) base to form the physical address, then accesses the operand from memory.

• The 16-bit offset is part of the instruction; the segment defaults to DS (unless a segment override is used).
• Physical address = DS × 10H + offset.

Examples:

MOV AX, [5000H]   ; AX <- contents of memory at DS:5000H
MOV [1234H], BL   ; store BL at offset 1234H in DS
MOV CL, COUNT     ; COUNT is a label = a direct memory offset

If DS = 2000H and the offset is 5000H, the physical address is 2000H × 10H + 5000H = 25000H.

Features:

• The operand's address (not the data) is fixed in the instruction.
• Simple and fast for accessing a known/fixed memory location.
• Contrasts with immediate mode (data in instruction) and register indirect mode (address held in a register such as BX/SI/DI).