BE Civil Engineering (IOE, TU) Basic Electronics Engineering (IOE, EX 451) Question Paper 2080 Nepal

(a) Depletion region and biasing

When a p-type and n-type semiconductor form a junction, free electrons from the n-side diffuse into the p-side and holes diffuse from the p-side into the n-side, where they recombine. This leaves behind immobile ionised donor atoms (positive) on the n-side and immobile ionised acceptor atoms (negative) on the p-side. This charged, carrier-free zone is the depletion region, and the resulting internal field produces a barrier potential ($\approx 0.7\,\text{V}$ for Si, $0.3\,\text{V}$ for Ge).

  p-side            n-side
 [ - - - | + + + ]
  acceptor  donor ions
   <-- depletion -->
   E-field points n -> p

• Forward bias (p to +, n to -): the external field opposes the internal field, the barrier potential is reduced, the depletion width narrows, and majority carriers cross, giving a large current.
• Reverse bias (p to -, n to +): the external field aids the internal field, the barrier potential is increased, the depletion width widens, and only a small reverse saturation current flows.

(b) Bridge rectifier with capacitor filter

Peak secondary voltage:

$$V_{m} = \sqrt{2}\,V_{rms} = 1.4142 \times 24 = 33.94\,\text{V}$$

(i) Peak load voltage — in a bridge, two diodes conduct in series each half cycle:

$$V_{peak} = V_m - 2V_F = 33.94 - 2(0.7) = 33.94 - 1.4 = \mathbf{32.54\,V}$$

(ii) DC load current — for a lightly-rippled output the average is close to the peak:

$$I_{DC} = \frac{V_{peak}}{R_L} = \frac{32.54}{470} = 0.06924\,\text{A} = \mathbf{69.2\,mA}$$

(iii) Ripple — full-wave ripple frequency $f_r = 2 \times 50 = 100\,\text{Hz}$.

$$V_{r(pp)} = \frac{I_{DC}}{f_r\,C} = \frac{0.06924}{100 \times 1000\times10^{-6}} = \frac{0.06924}{0.1} = \mathbf{0.692\,V}$$

RMS ripple $V_{r(rms)} = \dfrac{V_{r(pp)}}{2\sqrt{3}} = \dfrac{0.692}{3.464} = 0.1998\,\text{V}$.

Ripple factor:

$$r = \frac{V_{r(rms)}}{V_{DC}} = \frac{0.1998}{32.54} = 0.00614 = \mathbf{0.61\%}$$

(a) Voltage-divider bias and stability

        +Vcc
         |
   +-----+-----+
   |           |
  [R1]        [Rc]
   |           |
   +---B     C-+
   |    \   /
  [R2]   (NPN)
   |    /   \
  GND  E     
         |
        [Re]
         |
        GND

The divider $R_1$-$R_2$ fixes the base voltage $V_B$ almost independently of the transistor. The emitter resistor $R_E$ provides negative feedback: if $I_C$ (hence $I_E$) rises due to a higher $\beta$ or temperature, the emitter voltage $V_E = I_E R_E$ rises, which reduces $V_{BE}=V_B-V_E$, which in turn reduces $I_B$ and brings $I_C$ back down. Because $V_B$ is set by resistors and not by $\beta$, the Q-point is largely independent of $\beta$, unlike fixed-base bias where $I_B = (V_{CC}-V_{BE})/R_B$ is fixed and $I_C=\beta I_B$ tracks $\beta$ directly.

(b) Exact (Thevenin) analysis

Thevenin voltage and resistance at the base:

$$V_{TH} = V_{CC}\frac{R_2}{R_1+R_2} = 18 \times \frac{10}{49} = 3.673\,\text{V}$$ $$R_{TH} = R_1 \parallel R_2 = \frac{39 \times 10}{49} = 7.959\,\text{k}\Omega$$

Base loop (KVL):

$$I_B = \frac{V_{TH} - V_{BE}}{R_{TH} + (\beta+1)R_E} = \frac{3.673 - 0.7}{7.959\text{k} + 121\times1\text{k}}$$ $$I_B = \frac{2.973}{128.96\,\text{k}} = 23.06\,\mu\text{A}$$

Collector current:

$$I_C = \beta I_B = 120 \times 23.06\,\mu\text{A} = \mathbf{2.767\,mA}$$

Collector-emitter voltage (with $I_E \approx I_C$):

$$V_{CE} = V_{CC} - I_C(R_C + R_E) = 18 - 2.767\text{m}(2.2\text{k}+1\text{k})$$ $$V_{CE} = 18 - 2.767\text{m}\times 3200 = 18 - 8.854 = \mathbf{9.15\,V}$$

Region: $V_{CE}=9.15\,\text{V}$ is well above $V_{CE(sat)}$ and below $V_{CC}$, and the B-E junction is forward biased, so the transistor operates in the active region (a good Q-point near mid-supply, ideal for amplification).

(a) Ideal op-amp characteristics & virtual ground

Ideal op-amp properties:

• Infinite open-loop gain ($A_{OL}\to\infty$)
• Infinite input impedance (zero input current)
• Zero output impedance
• Infinite bandwidth and infinite slew rate
• Zero offset voltage; infinite CMRR

Virtual ground: In an inverting amplifier the non-inverting input is tied to ground (0 V). Because the open-loop gain is infinite, the differential input voltage must be essentially zero, so the inverting input sits at the same potential as the non-inverting input, i.e. $\approx 0\,\text{V}$. It is a "virtual" ground because it is held at 0 V by feedback without being physically connected to ground, and no current flows into the op-amp input.

(b) Inverting summing amplifier

With the inverting node at virtual ground, the currents through the input resistors sum into the feedback resistor:

$$\frac{V_1}{R_1} + \frac{V_2}{R_2} + \frac{V_3}{R_3} = -\frac{V_{out}}{R_f}$$

(i) Output expression:

$$V_{out} = -\left(\frac{R_f}{R_1}V_1 + \frac{R_f}{R_2}V_2 + \frac{R_f}{R_3}V_3\right)$$

Gains: $R_f/R_1 = 100/20 = 5$; $R_f/R_2 = 100/50 = 2$; $R_f/R_3 = 100/100 = 1$.

$$V_{out} = -\big(5(0.4) + 2(-1.0) + 1(2.0)\big)$$ $$V_{out} = -\big(2.0 - 2.0 + 2.0\big) = -\big(2.0\big) = \mathbf{-2.0\,V}$$

(ii) Clipping check: The output magnitude $|{-2.0}|\,\text{V}$ lies well within the $\pm12\,\text{V}$ rails (typical saturation $\approx \pm10.5\,\text{V}$). Therefore the output is not clipped and the amplifier operates linearly.

(a) K-map simplification

Plot the minterms 0,1,2,5,8,9,10 on a 4-variable map (rows $AB$, columns $CD$ in Gray order 00,01,11,10):

            CD=00  CD=01  CD=11  CD=10
 AB=00       1(0)   1(1)   0(3)   1(2)
 AB=01       0(4)   1(5)   0(7)   0(6)
 AB=11       0(12)  0(13)  0(15)  0(14)
 AB=10       1(8)   1(9)   0(11)  1(10)

Groupings:

• Group 1 (quad): minterms 0,1,8,9 -> $B=0$, $C=0$ -> term $B'C'$.
• Group 2 (quad): minterms 0,2,8,10 -> $B=0$, $D=0$ -> term $B'D'$.
• Group 3 (pair): minterms 1,5 -> $A=0,C=0,D=1$ -> term $A'C'D$.

Minimal SOP:

$$\boxed{F = B'C' + B'D' + A'C'D}$$

Check: $B'C'$ covers 0,1,8,9; $B'D'$ covers 0,2,8,10; $A'C'D$ covers 1,5. All seven minterms covered, no extras.

(b) NAND-only implementation

A SOP form maps directly to NAND-NAND. Each product term needs the variables ANDed; with 2-input NAND gates:

• $B'C'$: 1 NAND (inputs $B',C'$) giving $(B'C')'$.
• $B'D'$: 1 NAND giving $(B'D')'$.
• $A'C'D$ (3 literals): need $C'D$ via 1 NAND + inverter, then combine — using 2-input gates: NAND($C',D$)=$(C'D)'$, invert to $C'D$ (1 NAND as inverter), NAND($A',C'D$)=$(A'C'D)'$ -> 3 NANDs.
• Final OR of three terms $=$ NAND of their complements. With 2-input gates the three complemented terms are combined: NAND of first two complements, then a final stage — output stage = 1 NAND (2-input) combining two, plus 1 more to merge the third, effectively 2 NANDs.

Inverters for complemented inputs $A',B',C',D'$ where not already available: 4 NANDs used as inverters.

Total $\approx 11$ two-input NAND gates (1 + 1 + 3 for products, 2 for the output OR stage, 4 for input inverters). The exact count depends on how many complemented literals are supplied externally; if $A',B',C',D'$ are available, only 7 NAND gates are needed (1+1+3 product + 2 output stage).

(a) Instrumentation system block diagram

[Measurand] -> [Sensor/Transducer] -> [Signal Conditioning] -> [Signal Processing] -> [Display/Record/Output]

• Sensor/Transducer: converts the physical measurand (temperature, pressure, strain) into an electrical signal.
• Signal conditioning: amplifies, filters, linearises and converts the raw transducer signal (e.g. bridge + instrumentation amplifier) into a usable form.
• Signal processing: performs analog-to-digital conversion, computation, scaling, and calibration.
• Display / recording / output: presents the result to the observer or to a control system (meter, screen, data logger).

(b) Strain-gauge Wheatstone bridge

Change in gauge resistance:

$$\frac{\Delta R}{R} = GF \times \varepsilon = 2.0 \times 1500\times10^{-6} = 3.0\times10^{-3}$$ $$\Delta R = 0.003 \times 120 = \mathbf{0.36\,\Omega}$$

So $R_4 = 120 + 0.36 = 120.36\,\Omega$.

Bridge output (quarter bridge, output between the two midpoints):

$$V_o = V_s\left(\frac{R_3}{R_3+R_4} - \frac{R_2}{R_1+R_2}\right)$$ $$V_o = 5\left(\frac{120}{120+120.36} - \frac{120}{240}\right) = 5\left(\frac{120}{240.36} - 0.5\right)$$ $$\frac{120}{240.36} = 0.499251 \Rightarrow V_o = 5(0.499251 - 0.5) = 5(-0.000749)$$ $$V_o = -0.003744\,\text{V} = \mathbf{-3.74\,mV}$$

The magnitude of the bridge output is 3.74 mV (the sign indicates polarity due to the increase in $R_4$). A useful approximation $V_o \approx \frac{V_s}{4}\cdot\frac{\Delta R}{R} = \frac{5}{4}\times0.003 = 3.75\,\text{mV}$ confirms the result.

Load current (constant, since $V_L = V_Z = 6.2\,\text{V}$):

$$I_L = \frac{V_Z}{R_L} = \frac{6.2}{1000} = 6.2\,\text{mA}$$

Series (source) current depends on input voltage:

$$I_s = \frac{V_{in} - V_Z}{R_s}$$

At $V_{in}=10\,\text{V}$:

$$I_s = \frac{10 - 6.2}{220} = \frac{3.8}{220} = 17.27\,\text{mA}$$

At $V_{in}=14\,\text{V}$:

$$I_s = \frac{14 - 6.2}{220} = \frac{7.8}{220} = 35.45\,\text{mA}$$

Zener current $I_Z = I_s - I_L$:

• Minimum (at $V_{in}=10\,\text{V}$): $I_{Z,min} = 17.27 - 6.2 = \mathbf{11.07\,mA}$
• Maximum (at $V_{in}=14\,\text{V}$): $I_{Z,max} = 35.45 - 6.2 = \mathbf{29.25\,mA}$

Comment: $I_{Z,min}=11.07\,\text{mA} > 0$, so the Zener never falls out of breakdown across the whole input range; therefore regulation is maintained and the output stays at $6.2\,\text{V}$, provided the Zener's power rating exceeds $P_{Z,max}=V_Z I_{Z,max}=6.2\times29.25\text{m}=181\,\text{mW}$.

Transconductance / emitter resistance:

$$r_e = \frac{V_T}{I_E} \approx \frac{V_T}{I_C} = \frac{25\,\text{mV}}{1.5\,\text{mA}} = 16.67\,\Omega$$ $$r_\pi = (\beta+1) r_e \approx \beta r_e = 150 \times 16.67 = 2500\,\Omega = \mathbf{2.5\,k\Omega}$$

AC collector load (with bypassed emitter):

$$R_{ac} = R_C \parallel R_L = \frac{4.7 \times 10}{4.7 + 10} = \frac{47}{14.7} = 3.197\,\text{k}\Omega$$

Voltage gain (CE with fully bypassed emitter):

$$A_v = -\frac{R_{ac}}{r_e} = -\frac{3197}{16.67} = \mathbf{-191.8}$$

The magnitude is about 192, and the negative sign shows the $180^\circ$ phase inversion characteristic of the CE stage.

Input resistance into the base: $R_{in(base)} = r_\pi = \mathbf{2.5\,k\Omega}$ (the bias resistors would appear in parallel for the full stage input resistance).

(a) Non-inverting amplifier

$$A_v = 1 + \frac{R_f}{R_1} = 1 + \frac{47}{2.2} = 1 + 21.36 = \mathbf{22.36}$$

Output voltage:

$$V_{out} = A_v \times V_{in} = 22.36 \times 150\,\text{mV} = 3354\,\text{mV} = \mathbf{3.35\,V}$$

(b) Op-amp integrator

$$V_{out}(t) = -\frac{1}{RC}\int_0^t V_{in}\,dt = -\frac{V_{in}}{RC}\,t \quad (V_{in}\text{ constant})$$

Time constant:

$$RC = 10\times10^{3} \times 0.1\times10^{-6} = 1\times10^{-3}\,\text{s} = 1\,\text{ms}$$ $$V_{out} = -\frac{1\,\text{V}}{1\,\text{ms}} \times 5\,\text{ms} = -1 \times 5 = \mathbf{-5\,V}$$

The output ramps negatively (the integrator inverts), reaching $-5\,\text{V}$ at $t=5\,\text{ms}$ (assuming it has not yet hit the supply rail).

(a) Decimal conversions

To binary (divide by 2):

$$173 = 128 + 32 + 8 + 4 + 1 = 2^7+2^5+2^3+2^2+2^0$$ $$(173)_{10} = \mathbf{(10101101)_2}$$

To hexadecimal: group the binary in nibbles $1010\;1101 = \text{A}\;\text{D}$, or $173 = 10\times16 + 13$:

$$(173)_{10} = \mathbf{(\text{AD})_{16}}$$

(b) 8-bit 2's complement subtraction $45 - 29$

$45 = 0010\,1101_2$

$29 = 0001\,1101_2$

2's complement of 29: invert $\to 1110\,0010$, add 1 $\to 1110\,0011$.

Add:

   0010 1101   (+45)
 + 1110 0011   (-29)
 -----------
  1 0001 0000

The carry-out of the MSB is discarded, leaving $0001\,0000_2 = \mathbf{16}$.

Verification: $0001\,0000_2 = 16_{10}$, and $45 - 29 = 16$. The MSB is 0 (positive) and the result is correct.

(a) 4-to-1 Multiplexer

A 4-to-1 MUX routes one of four data inputs ($I_0$-$I_3$) to a single output $Y$ according to two select lines $S_1 S_0$. Output expression:

$$Y = \bar S_1\bar S_0 I_0 + \bar S_1 S_0 I_1 + S_1\bar S_0 I_2 + S_1 S_0 I_3$$

The selected channel is connected to the output; the others are blocked. It acts as a digitally controlled selector switch.

(b) Implementing $F = A\oplus B$

Use $A,B$ as the select lines ($S_1 = A$, $S_0 = B$). The XOR truth table is:

Set the data inputs equal to the required output for each select combination:

$$I_0 = 0,\quad I_1 = 1,\quad I_2 = 1,\quad I_3 = 0$$

Wiring $I_0=I_3=0$ (ground) and $I_1=I_2=1$ ($V_{CC}$) makes the MUX output reproduce the XOR function directly, with no extra gates.

(a) Resolution and quantisation error

Number of steps for $n=8$ bits: $2^8 = 256$ levels, i.e. $2^8 - 1 = 255$ intervals.

Resolution (step size):

$$Q = \frac{V_{FS}}{2^n - 1} = \frac{10}{255} = 0.03922\,\text{V} = \mathbf{39.22\,mV}$$

(Using $2^n$ steps gives $10/256 = 39.06\,\text{mV}$; either convention is acceptable.)

Maximum quantisation error is half a step:

$$e_q = \frac{Q}{2} = \frac{39.22}{2} = \mathbf{19.6\,mV}$$

(b) Digital output for $6.8\,\text{V}$

$$\text{Code} = \text{round}\!\left(\frac{V_{in}}{Q}\right) = \text{round}\!\left(\frac{6.8}{0.03922}\right) = \text{round}(173.4) = 173$$

Decimal output $= \mathbf{173}$.

Binary ($8$ bits): $173 = 128+32+8+4+1$

$$\Rightarrow (173)_{10} = \mathbf{(10101101)_2}$$

This corresponds to a reconstructed voltage of $173 \times 0.03922 = 6.785\,\text{V}$, within one step of the input.