BE Civil Engineering (IOE, TU) Basic Electronics Engineering (IOE, EX 451) Question Paper 2078 Nepal

(a) Depletion region

When a p-type and an n-type semiconductor are joined, the high concentration of free electrons on the n-side and holes on the p-side causes diffusion across the junction. Electrons diffuse into the p-side and recombine with holes; holes diffuse into the n-side and recombine with electrons. This leaves behind immobile ionized dopant atoms — negative acceptor ions on the p-side and positive donor ions on the n-side.

This region, now devoid of free carriers, is the depletion region. The exposed ions set up an internal electric field (a barrier potential, about $0.7\ \text{V}$ for Si) that opposes further diffusion, establishing equilibrium.

• Forward bias (p to +, n to −): the external field opposes the barrier field, the depletion region narrows, the barrier potential is reduced, and majority carriers cross easily → large current.
• Reverse bias (p to −, n to +): the external field aids the barrier field, the depletion region widens, the barrier increases, and only a tiny reverse saturation current (minority carriers) flows.

(b) Full-wave bridge rectifier with capacitor filter

Given: $V_{rms}=18\ \text{V}$, $f=50\ \text{Hz}$, $C=470\ \mu\text{F}$, $R_L=1.2\ \text{k}\Omega$, two diodes conduct per half-cycle ($2\times0.7=1.4\ \text{V}$ drop).

(i) Peak load voltage

$$V_m = \sqrt{2}\,V_{rms} = 1.4142 \times 18 = 25.46\ \text{V}$$ $$V_{peak,load} = V_m - 2V_D = 25.46 - 1.4 = \mathbf{24.06\ V}$$

(ii) DC load current (using the peak as the approximate average for a lightly-rippled filter)

$$I_{DC} = \frac{V_{peak,load}}{R_L} = \frac{24.06}{1200} = 0.02005\ \text{A} = \mathbf{20.05\ mA}$$

(iii) Peak-to-peak ripple voltage (full-wave: ripple frequency $=2f=100\ \text{Hz}$)

$$V_{r(pp)} = \frac{I_{DC}}{2 f C} = \frac{0.02005}{2 \times 50 \times 470\times10^{-6}} = \frac{0.02005}{0.047} = \mathbf{0.4266\ V}$$

(iv) Ripple factor

$$V_{r(rms)} = \frac{V_{r(pp)}}{2\sqrt{3}} = \frac{0.4266}{3.4641} = 0.1232\ \text{V}$$ $$r = \frac{V_{r(rms)}}{V_{DC}} = \frac{0.1232}{24.06} = 0.00512 = \mathbf{0.51\%}$$

The small ripple factor confirms effective smoothing by the $470\ \mu\text{F}$ capacitor.

(a) Thevenin (exact) analysis

Thevenin voltage at the base:

$$V_{TH} = V_{CC}\frac{R_2}{R_1+R_2} = 15 \times \frac{10}{47+10} = 15 \times \frac{10}{57} = 2.632\ \text{V}$$

Thevenin resistance:

$$R_{TH} = R_1\,\|\,R_2 = \frac{47\times10}{47+10} = \frac{470}{57} = 8.246\ \text{k}\Omega$$

Base loop (KVL): $V_{TH} = I_B R_{TH} + V_{BE} + I_E R_E$, with $I_E=(\beta+1)I_B$.

$$I_B = \frac{V_{TH}-V_{BE}}{R_{TH}+(\beta+1)R_E} = \frac{2.632-0.7}{8.246\text{k}+(121)(1\text{k})}$$ $$I_B = \frac{1.932}{8.246+121\ (\text{k}\Omega)} = \frac{1.932}{129.246\ \text{k}\Omega} = 14.95\ \mu\text{A}$$

Collector current:

$$I_C = \beta I_B = 120 \times 14.95\ \mu\text{A} = \mathbf{1.794\ mA}$$

Emitter current: $I_E = I_C + I_B = 1.794 + 0.0149 = 1.809\ \text{mA}$

Collector-emitter voltage:

$$V_{CE} = V_{CC} - I_C R_C - I_E R_E = 15 - (1.794\text{m})(2.2\text{k}) - (1.809\text{m})(1\text{k})$$ $$V_{CE} = 15 - 3.947 - 1.809 = \mathbf{9.24\ V}$$

Q-point: $I_C \approx 1.79\ \text{mA}$, $V_{CE} \approx 9.24\ \text{V}$.

(b) DC load line and Q-point

DC load-line equation: $V_{CE}=V_{CC}-I_C(R_C+R_E)$.

• Saturation (x-axis cut, $V_{CE}=0$): $I_{C(sat)}=\dfrac{V_{CC}}{R_C+R_E}=\dfrac{15}{3.2\text{k}}=4.69\ \text{mA}$
• Cut-off (y-axis cut, $I_C=0$): $V_{CE}=V_{CC}=15\ \text{V}$

 I_C (mA)
 4.69 |*
      | \
 1.79 |---* Q (9.24 V, 1.79 mA)
      |    \
    0 +-----*----- V_CE (V)
      0    9.24  15

Comment: $V_{CE}=9.24\ \text{V}$ is close to mid-supply ($V_{CC}/2=7.5\ \text{V}$) and $I_C$ sits roughly mid-way along the load line. The Q-point lies in the active region, well away from saturation and cut-off, giving good symmetrical voltage swing — the transistor is suitably biased for linear amplifier operation. The emitter resistor $R_E$ provides stable bias (DC negative feedback) against $\beta$ and temperature variation.

(a) Ideal op-amp properties

1. Infinite open-loop voltage gain ($A_{OL}\to\infty$).
2. Infinite input impedance ($Z_{in}\to\infty$, so input currents are zero).
3. Zero output impedance ($Z_{out}\to 0$).
4. Infinite bandwidth and infinite CMRR; zero input offset.

Virtual short: With negative feedback and very large $A_{OL}$, the differential input voltage $V_d=V_o/A_{OL}\to 0$. Hence $V_+ \approx V_-$: the two input terminals are at (almost) the same potential — a virtual short. When the non-inverting input is grounded, the inverting input becomes a virtual ground ($0\ \text{V}$) without actually drawing current.

(b) Inverting summing amplifier

$$V_o = -R_f\left(\frac{V_1}{R_1}+\frac{V_2}{R_2}+\frac{V_3}{R_3}\right)$$ $$V_o = -80\text{k}\left(\frac{0.4}{10\text{k}}+\frac{-0.6}{20\text{k}}+\frac{1.0}{40\text{k}}\right)$$

Compute each term:

• $\dfrac{0.4}{10\text{k}}=40\ \mu\text{A}$
• $\dfrac{-0.6}{20\text{k}}=-30\ \mu\text{A}$
• $\dfrac{1.0}{40\text{k}}=25\ \mu\text{A}$

Sum $=40-30+25=35\ \mu\text{A}$.

$$V_o = -80\times10^3 \times 35\times10^{-6} = -2.8\ \text{V}$$ $$\boxed{V_o = \mathbf{-2.8\ V}}$$

(c) Non-inverting gain from dB

$$A_{CL}(\text{dB})=26 \Rightarrow A_{CL}=10^{26/20}=10^{1.3}=19.95 \approx 20$$

For a non-inverting amplifier $A_{CL}=1+\dfrac{R_f}{R_1}$, so

$$\frac{R_f}{R_1}=A_{CL}-1 = 20-1 = \mathbf{19}$$

(The open-loop gain of $2\times10^5 \gg A_{CL}$, so the ideal closed-loop expression is valid.)

(a) Karnaugh map simplification

Minterms present (=1): 0,1,2,5,8,9,10. K-map (rows = $AB$, columns = $CD$ in Gray order $00,01,11,10$):

           CD=00  CD=01  CD=11  CD=10
AB=00       1(0)   1(1)   0(3)   1(2)
AB=01       0(4)   1(5)   0(7)   0(6)
AB=11       0(12)  0(13)  0(15)  0(14)
AB=10       1(8)   1(9)   0(11)  1(10)

Grouping:

1. Quad — minterms 0,1,8,9 (corners columns $CD=00,01$ with $AB=00,10$): here $B=0$ and $C=0$. Term = $\bar{B}\,\bar{C}$.
2. Quad — minterms 0,2,8,10 (four corners, $CD=00,10$ with $AB=00,10$): here $B=0$ and $D=0$. Term = $\bar{B}\,\bar{D}$.
3. Pair — minterms 1,5 ($A=0,C=0,D=1$): term = $\bar{A}\,\bar{C}\,D$.

All 1-cells are covered (0,1,2,8,9,10 by the two quads; 5 by the pair, which also re-covers 1).

$$\boxed{F = \bar{B}\,\bar{C} + \bar{B}\,\bar{D} + \bar{A}\,\bar{C}\,D}$$

(b) NAND-only implementation

A two-level SOP maps directly to NAND-NAND. Using De Morgan, $F=\overline{\overline{(\bar B\bar C)}\cdot\overline{(\bar B\bar D)}\cdot\overline{(\bar A\bar C D)}}$.

Gate count (allowing inverters from NANDs, with 2-input NANDs):

• Inverters for $\bar A,\bar B,\bar C,\bar D$: 4 NANDs (each input tied together).
• Term $\bar B\bar C$ : 1 NAND.
• Term $\bar B\bar D$ : 1 NAND.
• Term $\bar A\bar C D$ (3 literals): needs a 3-input AND ≈ NAND→ with 2-input gates: ($\bar A\cdot\bar C$) via 1 NAND giving $\overline{\bar A\bar C}$, then combine with $D$. To keep the NAND-NAND structure each product term feeds a NAND producing its complement. For the 3-literal term we form $\bar A\bar C$ (1 NAND + 1 inverter = 2 gates) then NAND that with $D$ → 1 gate.
• Final OR is realized as one NAND of the three term-complements: 1 NAND (3-input, or built from 2 two-input NANDs).

Practical 2-input NAND count: 4 (inverters) + 1 ($\bar B\bar C$) + 1 ($\bar B\bar D$) + 2 (3-literal term) + 1 (re-invert that term) + 2 (final 3-input OR-as-NAND from two 2-input NANDs) ≈ 11 two-input NAND gates.

If 3-input NANDs are permitted the design collapses to a clean two-level NAND-NAND network using 3 first-level NANDs + 1 output NAND + 4 inverters = 8 gates.

Diagram (logic):

A,B,C,D -> [inverters] -> Bbar,Cbar,Dbar,Abar
  Bbar,Cbar -> NAND -> g1
  Bbar,Dbar -> NAND -> g2
  Abar,Cbar,D -> NAND -> g3
  g1,g2,g3 -> NAND -> F

(a) Decibel gain, half-power frequencies, bandwidth

Voltage gain in dB: $A_v(\text{dB})=20\log_{10}(V_o/V_i)$; power gain in dB: $A_p(\text{dB})=10\log_{10}(P_o/P_i)$.

The half-power frequencies $f_L$ (lower) and $f_H$ (upper) are the frequencies at which output power falls to half its mid-band value, i.e. voltage gain falls to $1/\sqrt2=0.707$ of mid-band — equivalently a drop of $-3\ \text{dB}$. The bandwidth is $BW=f_H-f_L$, the band of frequencies over which the amplifier responds usefully (gain within 3 dB of mid-band).

(b) Numerical

Given $A_{mid}=250$, $f_L=40\ \text{Hz}$, $f_H=36\ \text{kHz}$.

(i) Mid-band gain in dB:

$$A(\text{dB})=20\log_{10}(250)=20\times2.3979 = \mathbf{47.96\ dB}$$

(ii) Bandwidth:

$$BW=f_H-f_L = 36000-40 = \mathbf{35960\ Hz}\;(\approx 35.96\ \text{kHz})$$

(iii) Gain at cut-off:

$$A_{cutoff}=0.707\times A_{mid}=0.707\times250 = \mathbf{176.8}$$

(equivalently $47.96-3 = 44.96\ \text{dB}$).

(iv) Gain-bandwidth product:

$$GBW = A_{mid}\times BW = 250 \times 35960 = 8.99\times10^{6}\ \text{Hz} = \mathbf{8.99\ MHz}$$

(c) Reasons for gain fall-off

• Low frequencies: the coupling and bypass capacitors have high reactance ($X_C=1/2\pi fC$). They no longer act as short circuits, so signal is dropped across them (and the emitter bypass becomes ineffective, reducing gain). This causes the low-frequency roll-off.
• High frequencies: the shunt (parasitic/junction) capacitances — transistor inter-electrode capacitances ($C_{be},C_{bc}$, Miller effect) and wiring/load capacitance — have low reactance and shunt the signal to ground, reducing gain. This causes the high-frequency roll-off.

Given $V_Z=6.2\ \text{V}$, $V_{in}=12\ \text{V}$, $R_s=220\ \Omega$, $R_L=1\ \text{k}\Omega$.

(i) Load current (load sees the regulated $V_Z$):

$$I_L = \frac{V_Z}{R_L} = \frac{6.2}{1000} = 6.2\ \text{mA} = \mathbf{6.2\ mA}$$

(ii) Series resistor current:

$$I_s = \frac{V_{in}-V_Z}{R_s} = \frac{12-6.2}{220} = \frac{5.8}{220} = 0.02636\ \text{A} = \mathbf{26.36\ mA}$$

(iii) Zener current (KCL: $I_s=I_Z+I_L$):

$$I_Z = I_s - I_L = 26.36 - 6.2 = \mathbf{20.16\ mA}$$

Verification: $I_Z = 20.16\ \text{mA} > I_{Z(min)}=5\ \text{mA}$, so the diode remains in breakdown and regulation is maintained.

(i) AC emitter resistance:

$$r_e = \frac{V_T}{I_E} = \frac{26\ \text{mV}}{1.5\ \text{mA}} = 17.33\ \Omega = \mathbf{17.33\ \Omega}$$

(ii) Voltage gain (fully bypassed CE: $A_v = -\dfrac{R_C\|R_L}{r_e}$):

AC collector load:

$$R_C\|R_L = \frac{3.3\times4.7}{3.3+4.7}\ \text{k}\Omega = \frac{15.51}{8}\ \text{k}\Omega = 1.939\ \text{k}\Omega$$ $$|A_v| = \frac{1939}{17.33} = \mathbf{111.9}$$

(The negative sign indicates $180^\circ$ phase inversion.)

(iii) Gain in dB:

$$A_v(\text{dB}) = 20\log_{10}(111.9) = 20\times2.0488 = \mathbf{40.98\ dB}$$

(a) Op-amp integrator

        R          C
Vin o--/\/\--+--||--+
            |       |
            |   |\  |
     (virtual    | \-+---o Vout
      ground) +--|+/
            |   |/
           GND

The input resistor $R$ feeds the inverting node (a virtual ground); the capacitor $C$ provides feedback. Since the input current $V_{in}/R$ flows entirely into $C$:

$$V_o(t) = -\frac{1}{RC}\int_0^t V_{in}\,dt + V_o(0)$$

A constant input gives a linearly ramping output — the circuit performs integration.

(b) Numerical

Time constant: $RC = (100\times10^3)(0.1\times10^{-6}) = 0.01\ \text{s} = 10\ \text{ms}$.

For a constant input $V_{in}=0.5\ \text{V}$, $V_o(0)=0$:

$$V_o(t) = -\frac{V_{in}}{RC}\,t = -\frac{0.5}{0.01}\,t = -50\,t \ \text{(V, with } t \text{ in s)}$$

Output after $20\ \text{ms}$:

$$V_o = -50 \times 0.020 = \mathbf{-1.0\ V}$$

Time to reach $-12\ \text{V}$:

$$-12 = -50\,t \;\Rightarrow\; t = \frac{12}{50} = 0.24\ \text{s} = \mathbf{240\ ms}$$

The output ramps negatively at $50\ \text{V/s}$ and saturates at $-12\ \text{V}$ after $240\ \text{ms}$.

(a) Conversions of $(214)_{10}$

Binary (repeated division by 2): $214\div2=107\ r0$; $107\div2=53\ r1$; $53\div2=26\ r1$; $26\div2=13\ r0$; $13\div2=6\ r1$; $6\div2=3\ r0$; $3\div2=1\ r1$; $1\div2=0\ r1$. Reading remainders bottom-up: $\mathbf{(11010110)_2}$.

Check: $128+64+16+4+2 = 214$. ✓

Octal (group binary in 3s from right: $11\,010\,110 \to 011\,010\,110$): $011=3,\ 010=2,\ 110=6 \Rightarrow \mathbf{(326)_8}$. Check: $3\times64+2\times8+6 = 192+16+6=214$. ✓

Hexadecimal (group in 4s: $1101\,0110$): $1101=D,\ 0110=6 \Rightarrow \mathbf{(D6)_{16}}$. Check: $13\times16+6 = 208+6=214$. ✓

(b) 2's-complement subtraction $(110101)_2-(10011)_2$

Decimal: $110101_2 = 53$, $10011_2 = 19$; expected $53-19=34$.

Use 6 bits. Minuend $=110101$. Subtrahend $=010011$ (padded). 2's complement of $010011$: invert $=101100$, add 1 $=101101$.

Add:

  110101
+ 101101
---------
 1100010

Discard the carry-out (7th bit) → result $=100010_2$.

$100010_2 = 32+2 = \mathbf{34_{10}}$. ✓ Matches $53-19=34$.

(a) Transducer

A transducer is a device that converts one form of energy/physical quantity into another, usually into an electrical signal proportional to the measured quantity.

• Active (self-generating): produces its own output (no external supply needed). Example: a thermocouple (generates emf from temperature), or a piezoelectric crystal.
• Passive (externally powered): requires an external excitation; the measurand modulates a circuit parameter (R, L, C). Example: a strain gauge (resistance changes with strain), or an RTD/LVDT.

(b) Strain-gauge Wheatstone bridge

Given $R=120\ \Omega$, gauge factor $GF=2.0$, $V_{ex}=5\ \text{V}$, strain $\varepsilon=1500\ \mu\varepsilon = 1500\times10^{-6}=1.5\times10^{-3}$.

(i) Change in resistance:

$$\frac{\Delta R}{R}=GF\times\varepsilon = 2.0 \times 1.5\times10^{-3} = 3\times10^{-3}$$ $$\Delta R = 120 \times 3\times10^{-3} = \mathbf{0.36\ \Omega}$$

(ii) Quarter-bridge output (one active arm):

$$V_o \approx \frac{V_{ex}}{4}\cdot\frac{\Delta R}{R} = \frac{5}{4}\times 3\times10^{-3} = 1.25 \times 3\times10^{-3}$$ $$V_o = 3.75\times10^{-3}\ \text{V} = \mathbf{3.75\ mV}$$

(a) Combinational vs sequential logic

(b) JK flip-flop

The JK flip-flop is a refinement of the SR flip-flop in which the forbidden $S=R=1$ condition is redefined as a useful toggle. Internal feedback of the outputs $Q,\bar Q$ back to the input gates ensures that when $J=K=1$ the output simply complements on each clock edge.

Truth table (clocked, edge $\downarrow$/$\uparrow$):

Overcoming the SR limitation: In an SR flip-flop the input combination $S=R=1$ is invalid (indeterminate output). The JK flip-flop uses output feedback so that $J=K=1$ produces a defined, predictable toggle ($Q_{n+1}=\bar Q_n$) instead of an illegal state — giving the device a complete, unambiguous truth table.