BE Civil Engineering (IOE, TU) Basic Electronics Engineering (IOE, EX 451) Question Paper 2076 Nepal

(a) Unbiased p-n junction

When p-type and n-type semiconductors are joined, free electrons from the n-side diffuse into the p-side and holes from the p-side diffuse into the n-side. Near the junction these majority carriers recombine, leaving behind immobile ionised donor atoms (positive) on the n-side and immobile acceptor atoms (negative) on the p-side. This charged, carrier-free zone is the depletion region.

   p-side                 n-side
  - - - - | + + + +
  - - - - | + + + +   <-- immobile ions
  - - - - | + + + +
          ^
      depletion region (no free carriers)
  <----- E (built-in field) -----

The separated charge sets up an internal electric field that opposes further diffusion; the associated potential is the barrier (built-in) potential, about $0.7\ \text{V}$ for silicon and $0.3\ \text{V}$ for germanium at room temperature.

V-I characteristic (silicon):

• Forward bias (p positive): once the applied voltage exceeds the knee/cut-in voltage ($\approx 0.7\ \text{V}$), the barrier collapses and current rises sharply and almost exponentially:

$$I = I_S\left(e^{V/\eta V_T} - 1\right)$$

• Reverse bias (p negative): the barrier widens; only a very small reverse saturation current $I_S$ flows until the breakdown voltage is reached, where reverse current increases steeply.

   I |            /  (forward)
     |           /
     |          /
 -----+--------+----------> V
  ___/| 0.7 V
 (reverse, small)

(b) Full-wave bridge rectifier

Given: $V_{rms}=24\ \text{V}$, $R_L=500\ \Omega$, two diodes conduct each half cycle so total drop $=2V_F=1.4\ \text{V}$, supply $50\ \text{Hz}$.

(i) Peak secondary voltage:

$$V_m = \sqrt{2}\times V_{rms} = 1.414\times 24 = 33.94\ \text{V}$$

Peak load voltage (subtract two diode drops):

$$V_{p(load)} = 33.94 - 1.4 = \mathbf{32.54\ V}$$

(ii) DC (average) load voltage for full-wave:

$$V_{DC} = \frac{2V_{p(load)}}{\pi} = \frac{2\times 32.54}{3.1416} = \mathbf{20.71\ V}$$

(iii) DC load current:

$$I_{DC} = \frac{V_{DC}}{R_L} = \frac{20.71}{500} = 0.04142\ \text{A} = \mathbf{41.42\ mA}$$

(iv) For a full-wave rectifier the ripple frequency is twice the supply frequency:

$$f_{ripple} = 2\times 50 = \mathbf{100\ Hz}$$

(a) npn transistor in active region

In the active region the base-emitter junction is forward biased and the base-collector junction is reverse biased. The forward-biased emitter junction injects electrons from the heavily doped emitter into the thin, lightly doped base. Most of these electrons diffuse across the base and are swept into the collector by the reverse-biased collector junction; only a small fraction recombine in the base, forming the base current.

Current relation (Kirchhoff at the transistor node):

$$I_E = I_B + I_C$$

Definitions:

• $\alpha = \dfrac{I_C}{I_E}$ (common-base current gain, < 1, typically 0.95–0.99)
• $\beta = \dfrac{I_C}{I_B}$ (common-emitter current gain, typically 50–300)

Derivation of $\beta=\dfrac{\alpha}{1-\alpha}$:

$$I_C = \alpha I_E = \alpha(I_B + I_C)$$ $$I_C - \alpha I_C = \alpha I_B$$ $$I_C(1-\alpha) = \alpha I_B$$ $$\beta = \frac{I_C}{I_B} = \frac{\alpha}{1-\alpha}\qquad\blacksquare$$

(b) Voltage-divider bias Q-point

Thévenin voltage at the base:

$$V_{TH} = V_{CC}\frac{R_2}{R_1+R_2} = 12\times\frac{10}{47+10} = 12\times 0.17544 = 2.105\ \text{V}$$

Thévenin resistance:

$$R_{TH} = R_1\Vert R_2 = \frac{47\times 10}{47+10} = \frac{470}{57} = 8.246\ \text{k}\Omega$$

Base loop (KVL):

$$V_{TH} = I_B R_{TH} + V_{BE} + I_E R_E,\quad I_E\approx(\beta+1)I_B$$ $$2.105 = I_B(8.246\ \text{k}) + 0.7 + (121)I_B(0.560\ \text{k})$$ $$2.105 - 0.7 = I_B(8.246 + 67.76)\ \text{k} = I_B(76.0\ \text{k})$$ $$I_B = \frac{1.405}{76.0\times10^{3}} = 18.49\ \mu\text{A}$$

Collector current:

$$I_C = \beta I_B = 120\times 18.49\ \mu\text{A} = 2.219\ \text{mA}\approx\mathbf{2.22\ mA}$$

Collector-emitter voltage ($I_E\approx I_C$):

$$V_{CE} = V_{CC} - I_C(R_C + R_E) = 12 - 2.219\ \text{mA}\times(1500+560)\ \Omega$$ $$V_{CE} = 12 - 2.219\ \text{mA}\times 2060\ \Omega = 12 - 4.571 = \mathbf{7.43\ V}$$

Q-point: $I_C \approx 2.22\ \text{mA}$, $V_{CE} \approx 7.43\ \text{V}$ — comfortably in the active region.

(a) Ideal op-amp characteristics

1. Infinite open-loop gain ($A_{OL}\to\infty$)
2. Infinite input impedance ($Z_{in}\to\infty$) → zero input current
3. Zero output impedance ($Z_{out}=0$)
4. Infinite bandwidth
5. Infinite common-mode rejection ratio (CMRR)
6. Zero input offset voltage; output = 0 when both inputs are equal

Virtual short / virtual ground: With negative feedback the output adjusts itself so that the differential input voltage is driven to (almost) zero. Hence $V_+ \approx V_-$ — the two inputs are at the same potential without being physically connected (a virtual short). When the non-inverting input is grounded ($V_+=0$), the inverting input is held at $0\ \text{V}$ — a virtual ground. Combined with zero input current, this lets us analyse the circuit by node equations at the inverting input.

(b) Inverting summing amplifier

The inverting input is a virtual ground (0 V). Sum of input currents equals feedback current:

$$\frac{V_1}{R_1}+\frac{V_2}{R_2}+\frac{V_3}{R_3} = -\frac{V_o}{R_f}$$ $$\boxed{V_o = -R_f\left(\frac{V_1}{R_1}+\frac{V_2}{R_2}+\frac{V_3}{R_3}\right)}$$

Gain per channel:

• $R_f/R_1 = 100/20 = 5$
• $R_f/R_2 = 100/50 = 2$
• $R_f/R_3 = 100/25 = 4$

Substitute:

$$V_o = -\big[5(0.5) + 2(1.0) + 4(-0.8)\big]$$ $$V_o = -\big[2.5 + 2.0 - 3.2\big] = -[1.3] = \mathbf{-1.3\ V}$$

Saturation check: $|{-1.3\ \text{V}}| < 12\ \text{V}$, so the output lies well within the $\pm 12\ \text{V}$ rails and does not saturate.

(a) De Morgan's theorems

1. $\overline{A+B} = \bar{A}\cdot\bar{B}$
2. $\overline{A\cdot B} = \bar{A}+\bar{B}$

Truth-table proof of theorem 1:

Columns $\overline{A+B}$ and $\bar A\cdot\bar B$ are identical for all input combinations, hence proved. $\blacksquare$

(b) K-map simplification

Minterms present: 0,1,2,5,8,9,10. Place 1s on the 4-variable map (rows AB, columns CD in Gray order 00,01,11,10):

           CD=00  CD=01  CD=11  CD=10
AB=00       1(0)   1(1)   0(3)   1(2)
AB=01       0(4)   1(5)   0(7)   0(6)
AB=11       0(12)  0(13)  0(15)  0(14)
AB=10       1(8)   1(9)   0(11)  1(10)

Grouping:

• Group 1 (quad): minterms 0,1,8,9 → $A$ and $B$ vary..., common: $B=0, C=0$ → term $\bar B\,\bar C$.
• Group 2 (quad): minterms 0,2,8,10 → common: $B=0, D=0$ → term $\bar B\,\bar D$.
• Group 3 (pair): minterms 1,5 → common: $A=0, C=0, D=1$ → term $\bar A\,\bar C\,D$.

Simplified expression:

$$\boxed{F = \bar B\,\bar C + \bar B\,\bar D + \bar A\,\bar C\,D}$$

Verification (spot check): m5 (A=0,B=1,C=0,D=1): $\bar B\bar C=0$, $\bar B\bar D=0$, $\bar A\bar C D = 1\cdot1\cdot1=1$ → F=1 ✓. m10 (1,0,1,0): $\bar B\bar D=1\cdot1=1$ → F=1 ✓. m3 (0,0,1,1): $\bar B\bar C=0$, $\bar B\bar D=0$, $\bar A\bar C D=1\cdot0\cdot1=0$ → F=0 ✓ (not a minterm).

Logic circuit (described):

• NOT gates produce $\bar A, \bar B, \bar C, \bar D$.
• AND gate 1: inputs $\bar B,\bar C$ → $\bar B\bar C$.
• AND gate 2: inputs $\bar B,\bar D$ → $\bar B\bar D$.
• AND gate 3: inputs $\bar A,\bar C, D$ → $\bar A\bar C D$.
• Final 3-input OR gate combines the three AND outputs to give $F$.

(a) Generalized instrumentation system

[Physical    ]   [Transducer/]   [Signal      ]   [Signal     ]   [Display /  ]
[quantity    ]-->[Sensor     ]-->[Conditioning]-->[Processing ]-->[Recording  ]

• Transducer/Sensor: converts the physical quantity (temperature, pressure, displacement) into an electrical signal (voltage, current, resistance change).
• Signal conditioning: amplifies, filters, linearises and converts the raw sensor signal into a usable form (e.g., bridge + instrumentation amplifier, filtering of noise).
• Signal processing: performs operations such as analog-to-digital conversion, scaling, computation, or comparison so the data can be interpreted.
• Display / Recording: presents the measured value to the observer (digital display, meter) or stores it (data logger, chart recorder).

(b) Wheatstone bridge

Bridge arms: $R_1, R_2$ in one branch, $R_3, R_x$ in the other (standard balance condition $R_1/R_2 = R_3/R_x$).

(i) Balance condition:

$$\frac{R_1}{R_2}=\frac{R_3}{R_x}\implies R_x = \frac{R_2 R_3}{R_1} = \frac{1000\times1000}{1000} = \mathbf{1000\ \Omega}$$

(ii) Off-balance output with $R_x = 1020\ \Omega$. Output is the difference between the two voltage-divider node voltages.

Node A (junction of $R_1$ and $R_2$):

$$V_A = V_s\frac{R_2}{R_1+R_2} = 10\times\frac{1000}{2000} = 5.000\ \text{V}$$

Node B (junction of $R_3$ and $R_x$):

$$V_B = V_s\frac{R_x}{R_3+R_x} = 10\times\frac{1020}{1000+1020} = 10\times\frac{1020}{2020} = 10\times0.50495 = 5.0495\ \text{V}$$

Output voltage:

$$V_o = V_B - V_A = 5.0495 - 5.000 = 0.0495\ \text{V} = \mathbf{49.5\ mV}$$

The positive off-balance voltage of about $49.5\ \text{mV}$ is the measure of the temperature-induced resistance change.

Given: $V_{in}=15\ \text{V}$, $V_Z=6.2\ \text{V}$, $R_S=220\ \Omega$, $I_L=20\ \text{mA}$.

(i) Series resistor current (voltage across $R_S$ is $V_{in}-V_Z$):

$$I_S = \frac{V_{in}-V_Z}{R_S} = \frac{15-6.2}{220} = \frac{8.8}{220} = 0.04\ \text{A} = \mathbf{40\ mA}$$

(ii) Zener current (KCL: $I_S = I_Z + I_L$):

$$I_Z = I_S - I_L = 40\ \text{mA} - 20\ \text{mA} = \mathbf{20\ mA}$$

(iii) Power dissipated in the Zener:

$$P_Z = V_Z\times I_Z = 6.2\ \text{V}\times 0.020\ \text{A} = 0.124\ \text{W} = \mathbf{124\ mW}$$

Given: $A_1=12$, $A_2=25$, $A_3=8$, $V_{in}=5\ \text{mV}$.

(i) Overall voltage gain (product of stage gains):

$$A_V = A_1\times A_2\times A_3 = 12\times 25\times 8 = 2400$$ $$\mathbf{A_V = 2400}$$

(ii) Gain in decibels:

$$A_{V(dB)} = 20\log_{10}(A_V) = 20\log_{10}(2400)$$ $$\log_{10}(2400) = 3.3802$$ $$A_{V(dB)} = 20\times 3.3802 = \mathbf{67.6\ dB}$$

(iii) Output voltage:

$$V_{out} = A_V\times V_{in} = 2400\times 5\ \text{mV} = 12000\ \text{mV} = \mathbf{12\ V}$$

(a) Non-inverting amplifier

Closed-loop gain:

$$A_V = 1 + \frac{R_f}{R_1} = 1 + \frac{90}{10} = 1 + 9 = \mathbf{10}$$

Output voltage:

$$V_o = A_V\times V_{in} = 10\times 0.2\ \text{V} = \mathbf{2\ V}$$

(The output is in phase with the input, a key feature of the non-inverting configuration.)

(b) Op-amp integrator

With input resistor $R$ and feedback capacitor $C$, the ideal output is:

$$\boxed{V_o(t) = -\frac{1}{RC}\int_0^t V_{in}\,dt + V_o(0)}$$

The output is proportional to the time integral of the input (with a sign inversion).

Application: waveform generation (e.g., converting a square wave into a triangular wave), analog computers solving differential equations, and ramp generators in analog-to-digital converters.

(i) Decimal 186 to binary and hex

Repeated division by 2: 186→93 r0, 93→46 r1, 46→23 r0, 23→11 r1, 11→5 r1, 5→2 r1, 2→1 r0, 1→0 r1. Reading remainders bottom-up:

$$(186)_{10} = \mathbf{(1011\,1010)_2}$$

Group into nibbles: $1011 = \text{B}$, $1010 = \text{A}$:

$$(186)_{10} = \mathbf{(BA)_{16}}$$

(Check: $11\times16 + 10 = 176 + 10 = 186$ ✓)

(ii) Binary addition $1011 + 1101$

   1011   (11)
 + 1101   (13)
 ------
  11000   (24)

Step: 1+1=10 (write 0 carry 1); 1+0+1=10 (write 0 carry 1); 0+1+1=10 (write 0 carry 1); 1+1+1=11 (write 1 carry 1); final carry 1.

$$(1011)_2 + (1101)_2 = \mathbf{(11000)_2} = 24_{10}$$

Verification: $11 + 13 = 24$ ✓

(iii) 2's complement of $0110\,1010$

1's complement (invert all bits): $0110\,1010 \to 1001\,0101$.

Add 1:

$$1001\,0101 + 1 = \mathbf{1001\,0110}$$

So the 2's complement is $(1001\,0110)_2$.

(a) NAND as a universal gate

NAND is called universal because any logic function (AND, OR, NOT) — and therefore any combinational circuit — can be implemented using only NAND gates.

OR using NAND: By De Morgan, $A + B = \overline{\bar A\cdot\bar B}$.

• NAND gate 1: inputs $A,A$ → $\bar A$
• NAND gate 2: inputs $B,B$ → $\bar B$
• NAND gate 3: inputs $\bar A,\bar B$ → $\overline{\bar A\bar B} = A + B$

Truth table:

The last column matches the OR truth table. ✓

(b) XOR gate

Boolean expression:

$$Y = A\oplus B = \bar A B + A\bar B$$

Truth table:

Output is HIGH only when the inputs differ.

(a) Active vs passive transducers

(b) LVDT working principle

An LVDT has one primary winding and two identical secondary windings (S1, S2) wound symmetrically on either side of the primary, with a movable ferromagnetic core. The primary is energised with AC. The core's position determines the magnetic coupling to each secondary.

• At the null (centre) position, equal flux links S1 and S2; since they are connected in series opposition, the net output $V_o = V_{S1} - V_{S2} = 0$.
• When the core moves toward S1, $V_{S1} > V_{S2}$, giving a net output whose magnitude is proportional to displacement and whose phase indicates the direction of movement.

Advantages:

1. Frictionless operation (no physical contact between core and windings) → high resolution and long life.
2. High sensitivity, good linearity over its range, and robust against shock/vibration.