BE Civil Engineering (IOE, TU) Basic Electronics Engineering (IOE, EX 451) Question Paper 2079 Nepal

(a) Depletion region in a P-N junction

When a P-type and an N-type semiconductor are joined, the high concentration of holes on the P-side and electrons on the N-side causes diffusion of majority carriers across the junction. Electrons crossing into the P-side recombine with holes, and holes crossing into the N-side recombine with electrons. This leaves behind immobile ionized dopant atoms: negative acceptor ions on the P-side and positive donor ions on the N-side.

This region, depleted of free charge carriers, is the depletion region. The exposed ions set up an internal electric field opposing further diffusion. Equilibrium is reached when the field is strong enough to stop net carrier flow.

• Barrier potential ($V_0$): the built-in potential difference across the depletion region at equilibrium. Approximately $0.7\text{ V}$ for silicon and $0.3\text{ V}$ for germanium at room temperature.
• Depletion width: the physical thickness of the carrier-free region. It narrows under forward bias and widens under reverse bias.

V-I characteristic (silicon):

      I (mA)
        |             /  (forward: steep rise after ~0.7 V)
        |            /
        |           /
  ------+----------+--------- V
   <----|         0.7 V
  (reverse: tiny leakage current,
   then sharp breakdown at -V_BR)
        |

• Forward bias: P to +, N to −. Barrier reduces; conduction begins near the knee voltage ($\approx 0.7\text{ V}$), after which current rises steeply.
• Reverse bias: only a small reverse saturation current ($I_S$) flows until the breakdown voltage, beyond which current increases sharply.

(b) Zener regulator analysis

The Zener carries the maximum current when the input is maximum and the load current is minimum.

Maximum Zener voltage stays clamped at $V_Z = 6.2\text{ V}$.

Current through the series resistor at $V_{in} = 16\text{ V}$:

$$I_S = \frac{V_{in(\max)} - V_Z}{R_S} = \frac{16 - 6.2}{120} = \frac{9.8}{120} = 0.08167\text{ A} = 81.67\text{ mA}$$

At this condition the load current is minimum, $I_{L(\min)} = 5\text{ mA}$:

$$I_{Z(\max)} = I_S - I_{L(\min)} = 81.67 - 5 = \mathbf{76.67\ mA}$$

Power dissipated in the Zener:

$$P_Z = V_Z \times I_{Z(\max)} = 6.2 \times 0.07667 = 0.475\text{ W}$$

Compare with rating: $P_{Z(\max)} = 0.5\text{ W}$.

Since $0.475\text{ W} < 0.5\text{ W}$, the Zener rating is not exceeded — the design is safe, but the margin is small (only $25\text{ mW}$, i.e. about 5%).

Final answers: $I_{Z(\max)} = \mathbf{76.67\ mA}$, $P_Z = \mathbf{0.475\ W} < 0.5\text{ W}$ — safe.

(a) Voltage-divider bias and stability

        +Vcc
         |
     +---+---+
     |       |
    R1      Rc
     |       |
     +---+---C (collector)
     |   |
     |   B---[NPN]
    R2   |   E
     |   |   |
     +---+   Re
     |       |
    GND-----+--- GND

$R_1$ and $R_2$ form a divider that fixes the base voltage $V_B$ nearly independent of base current. The emitter resistor $R_E$ provides negative feedback: if temperature or $\beta$ rises and $I_C$ tends to increase, the emitter voltage $V_E = I_E R_E$ rises, which reduces $V_{BE} = V_B - V_E$, thereby reducing $I_B$ and counteracting the increase in $I_C$. Because $V_B$ is set by the resistor ratio (not by $\beta$), the Q-point is largely independent of the transistor's $\beta$ — giving excellent stability.

(b) Q-point by exact Thevenin method

Thevenin voltage (base):

$$V_{TH} = V_{CC}\,\frac{R_2}{R_1 + R_2} = 15 \times \frac{10}{47 + 10} = 15 \times \frac{10}{57} = 2.632\text{ V}$$

Thevenin resistance:

$$R_{TH} = R_1 \parallel R_2 = \frac{47 \times 10}{47 + 10} = \frac{470}{57} = 8.246\ \text{k}\Omega$$

Base loop (KVL):

$$V_{TH} = I_B R_{TH} + V_{BE} + I_E R_E, \quad I_E = (\beta + 1)I_B$$ $$2.632 = I_B(8.246\text{k}) + 0.7 + I_B(121)(1\text{k})$$ $$2.632 - 0.7 = I_B(8.246\text{k} + 121\text{k})$$ $$1.932 = I_B(129.246\text{k})$$ $$I_B = \frac{1.932}{129246} = 14.95\ \mu\text{A}$$

Collector current:

$$I_{CQ} = \beta I_B = 120 \times 14.95\ \mu\text{A} = 1.794\text{ mA} \approx \mathbf{1.79\ mA}$$

Collector-emitter voltage: with $I_E \approx I_C$,

$$V_{CEQ} = V_{CC} - I_C(R_C + R_E) = 15 - 1.794\text{m}(2.2\text{k} + 1\text{k})$$ $$V_{CEQ} = 15 - 1.794\text{m}(3.2\text{k}) = 15 - 5.74 = \mathbf{9.26\ V}$$

Q-point: $I_{CQ} = \mathbf{1.79\ mA}$, $V_{CEQ} = \mathbf{9.26\ V}$.

(a) Ideal op-amp & inverting gain

Ideal assumptions:

1. Infinite open-loop gain ($A \to \infty$).
2. Infinite input impedance — no current flows into either input terminal.
3. Zero output impedance.

With negative feedback, the differential input voltage is forced to zero, so $V_- = V_+$ (virtual short). For an inverting amplifier the non-inverting input is grounded ($V_+ = 0$), hence $V_- = 0$ — a virtual ground.

  Vin --[R1]--+--[Rf]--+
              |        |
             (-)\      |
              |  >----+---- Vo
             (+)/
              |
             GND

Since no current enters the inverting input, the current through $R_1$ equals the current through $R_f$:

$$\frac{V_{in} - 0}{R_1} = \frac{0 - V_o}{R_f}$$ $$\boxed{A_v = \frac{V_o}{V_{in}} = -\frac{R_f}{R_1}}$$

(b) Summing amplifier output

For an inverting summer, each input contributes through its own gain:

$$V_o = -\left(\frac{R_f}{R_1}V_1 + \frac{R_f}{R_2}V_2 + \frac{R_f}{R_3}V_3\right)$$

Compute each gain:

• $R_f/R_1 = 60/20 = 3$
• $R_f/R_2 = 60/30 = 2$
• $R_f/R_3 = 60/12 = 5$

Substitute:

$$V_o = -\big(3(0.5) + 2(-1.2) + 5(0.8)\big)$$ $$V_o = -\big(1.5 - 2.4 + 4.0\big) = -\big(3.1\big) = \mathbf{-3.1\ V}$$

Clipping check: $|V_o| = 3.1\text{ V}$, which is well within the $\pm 12\text{ V}$ rails. The output is not clipped.

Final answer: $V_o = \mathbf{-3.1\ V}$ (no clipping).

(a) K-map simplification

Place 1s at the listed minterms. K-map (rows $AB$, columns $CD$ in Gray order $00,01,11,10$):

           CD=00  CD=01  CD=11  CD=10
  AB=00     1(0)   1(1)   0(3)   1(2)
  AB=01     0(4)   1(5)   0(7)   0(6)
  AB=11     0(12)  1(13)  0(15)  0(14)
  AB=10     1(8)   1(9)   0(11)  1(10)

Group 1 — the four corners + their column neighbours: minterms $0,2,8,10$ form a quad where $B=0$ and $D=0$ → term $\overline{B}\,\overline{D}$.

Group 2 — minterms $1,5,9,13$: here $C=0$ and $D=1$ across all four (these are the CD=01 column, all four rows have 1s) → term $\overline{C}D$.

Check coverage:

• $\overline{B}\,\overline{D}$ covers 0,2,8,10.
• $\overline{C}D$ covers 1,5,9,13.

All eight minterms covered.

$$\boxed{F = \overline{B}\,\overline{D} + \overline{C}\,D}$$

(b) NAND-only implementation

A two-level SOP maps directly to a NAND-NAND network. Rewrite using double negation:

$$F = \overline{\overline{(\overline{B}\,\overline{D})}\cdot\overline{(\overline{C}\,D)}}$$

Gate structure:

1. Generate complements $\overline{B}, \overline{C}, \overline{D}$ using NAND gates wired as inverters (both inputs tied together).
2. NAND-1: inputs $\overline{B}, \overline{D}$ → output $\overline{\overline{B}\,\overline{D}}$.
3. NAND-2: inputs $\overline{C}, D$ → output $\overline{\overline{C}\,D}$.
4. NAND-3 (output gate): inputs are outputs of NAND-1 and NAND-2 → produces $F$.

This realises the function with three 2-input NAND gates plus inverters (also NANDs), confirming the NAND-universal property.

(a) Transducer definitions

A transducer is a device that converts one form of energy (a physical quantity such as temperature, pressure, displacement or strain) into another form, usually an electrical signal proportional to the measured quantity, suitable for measurement, processing or control.

(b) Strain gauge in Wheatstone bridge

(i) Change in resistance. The gauge factor relates fractional resistance change to strain:

$$G_F = \frac{\Delta R / R}{\varepsilon} \;\Rightarrow\; \Delta R = G_F \cdot \varepsilon \cdot R$$

With $\varepsilon = 800\ \mu\varepsilon = 800 \times 10^{-6} = 8.0\times10^{-4}$:

$$\Delta R = 2.0 \times (8.0\times10^{-4}) \times 120 = 2.0 \times 0.096 = \mathbf{0.192\ \Omega}$$

(ii) Bridge output (quarter-bridge).

$$V_o \approx \frac{V_s}{4}\cdot\frac{\Delta R}{R} = \frac{5}{4}\times\frac{0.192}{120}$$ $$\frac{\Delta R}{R} = \frac{0.192}{120} = 1.6\times10^{-3}$$ $$V_o = 1.25 \times 1.6\times10^{-3} = 2.0\times10^{-3}\text{ V} = \mathbf{2.0\ mV}$$

Final answers: $\Delta R = \mathbf{0.192\ \Omega}$, bridge output $V_o \approx \mathbf{2.0\ mV}$.

(i) Peak load voltage. For a bridge rectifier (neglecting diode drops) the peak equals the secondary peak:

$$V_m = \sqrt{2}\,V_{rms} = 1.414 \times 12 = \mathbf{16.97\ V} \approx 17\text{ V}$$

(ii) DC load voltage with capacitor filter. Approximate DC value as $V_{dc} \approx V_m - \dfrac{V_{r(pp)}}{2}$. First estimate the load (DC) current using $V_m$:

$$I_{dc} \approx \frac{V_{dc}}{R_L}\approx \frac{V_m}{R_L} = \frac{16.97}{1000} = 16.97\text{ mA (first estimate)}$$

(iii) Peak-to-peak ripple. For a full-wave rectifier the ripple frequency is $2f = 100\text{ Hz}$:

$$V_{r(pp)} = \frac{I_{dc}}{2 f C} = \frac{16.97\times10^{-3}}{2 \times 50 \times 470\times10^{-6}}$$ $$= \frac{16.97\times10^{-3}}{0.047} = 0.361\text{ V} = \mathbf{0.36\ V}$$

Refined DC voltage:

$$V_{dc} \approx V_m - \frac{V_{r(pp)}}{2} = 16.97 - \frac{0.361}{2} = 16.97 - 0.18 = \mathbf{16.79\ V}$$

Final answers: $V_m \approx \mathbf{16.97\ V}$; $V_{dc} \approx \mathbf{16.79\ V}$; $V_{r(pp)} \approx \mathbf{0.36\ V}$.

(a) n-channel enhancement MOSFET

          Drain (D)
            |
   Gate ||==+
  (G)  ||   (oxide-insulated gate)
   ----||==+
            |
          Source (S)
   (Body/Substrate usually tied to S)

In an n-channel enhancement MOSFET the substrate is p-type with n-type source and drain diffusions. The metal/poly gate is insulated from the channel region by a thin silicon-dioxide layer (hence very high input impedance).

• With $V_{GS} = 0$ there is no conducting channel between drain and source (the device is normally OFF).
• When a positive $V_{GS}$ is applied, the gate field repels holes and attracts electrons to the surface beneath the oxide. Once $V_{GS}$ exceeds the threshold voltage $V_{GS(th)}$, an inversion layer (n-channel) forms, connecting source to drain and allowing $I_D$ to flow.
• Increasing $V_{GS}$ beyond $V_{GS(th)}$ enhances the channel and increases $I_D$ — hence "enhancement type." Drain current is controlled by the gate voltage.

(b) BJT vs FET — three differences

(Additional valid points: FETs are less noisy and more temperature-stable; BJTs offer higher transconductance/gain for a given size.)

(a) Non-inverting amplifier

Closed-loop gain of a non-inverting amplifier:

$$A_v = 1 + \frac{R_f}{R_1} = 1 + \frac{90\text{k}}{10\text{k}} = 1 + 9 = \mathbf{10}$$

Output voltage:

$$V_o = A_v \times V_{in} = 10 \times 0.2 = \mathbf{2.0\ V}$$

Note the output is in phase (non-inverting), so $V_o = +2.0\text{ V}$.

(b) Op-amp integrator

An integrator produces an output proportional to the time integral of the input signal. It is built by placing a capacitor $C$ in the feedback path of an inverting op-amp (with input resistor $R$). The virtual ground forces the input current $V_{in}/R$ to charge $C$, giving:

$$V_o(t) = -\frac{1}{RC}\int_0^{t} V_{in}\,dt + V_o(0)$$

Uses: waveform generation (e.g. ramp/triangular from a square wave), analog computation, and active low-pass filtering.

(a) Decimal conversions

To binary (repeated division by 2, remainders bottom-up):

$$173 = 128 + 32 + 8 + 4 + 1 = 2^7 + 2^5 + 2^3 + 2^2 + 2^0$$ $$(173)_{10} = (1010\,1101)_2$$

To hexadecimal (group binary in nibbles): $1010 = A$, $1101 = D$:

$$(173)_{10} = (\mathbf{AD})_{16}$$

Check: $A\times16 + D = 10\times16 + 13 = 160 + 13 = 173$. ✓

(b) 8-bit 2's complement subtraction $45 - 29$

Write the operands in 8-bit binary:

• $45 = (0010\,1101)_2$
• $29 = (0001\,1101)_2$

2's complement of 29: invert bits → $1110\,0010$, then add 1 → $1110\,0011$.

Add $45 + (-29)$:

   0010 1101   (45)
 + 1110 0011   (-29)
 -----------
  1 0001 0000

The carry out of the 8th bit is discarded. Result $= (0001\,0000)_2 = 16_{10}$.

Verification: $45 - 29 = 16$. The MSB is 0 (positive), the carry-out is discarded with no overflow (signs of operands differ → overflow impossible). ✓

Final answers: $(173)_{10} = (10101101)_2 = (AD)_{16}$; $45 - 29 = (00010000)_2 = \mathbf{16}$.

(a) Power gain in dB

$$A_{p(dB)} = 10\log_{10}\!\left(\frac{P_{out}}{P_{in}}\right) = 10\log_{10}\!\left(\frac{8}{2\times10^{-3}}\right)$$ $$\frac{8}{0.002} = 4000$$ $$A_{p(dB)} = 10\log_{10}(4000) = 10 \times 3.602 = \mathbf{36.02\ dB}$$

(b) Voltage gain in dB

$$A_{v(dB)} = 20\log_{10}(A_v) = 20\log_{10}(200) = 20 \times 2.301 = \mathbf{46.02\ dB}$$

(c) Bandwidth

The bandwidth (BW) of an amplifier is the range of frequencies over which the gain remains within $3\text{ dB}$ of its mid-band value (i.e. the gain does not fall below $1/\sqrt{2} = 0.707$ of mid-band gain, corresponding to half the output power).

It is defined by two cut-off (half-power) frequencies:

• Lower cut-off frequency $f_L$ — below which gain rolls off (limited by coupling/bypass capacitors).
• Upper cut-off frequency $f_H$ — above which gain rolls off (limited by device/stray capacitances).

$$\text{BW} = f_H - f_L$$

At $f_L$ and $f_H$ the power output is half the mid-band power, hence the name half-power frequencies.

(a) Combinational vs sequential

(b) JK flip-flop truth table

Operation: The JK flip-flop removes the forbidden ($J=K=1$) state of the SR flip-flop. With $J=0,K=0$ the output holds its previous value; $J=0,K=1$ forces a reset to 0; $J=1,K=0$ sets the output to 1. The key feature is the toggle condition: when $J=K=1$, on each active clock edge the output complements ($Q_{n+1} = \overline{Q_n}$). This toggling makes the JK flip-flop ideal for building counters and frequency dividers.

(c) MOD-16 ripple counter

A MOD-$N$ counter needs $n$ flip-flops where $2^n \ge N$. For MOD-16, $2^4 = 16$, so:

• Number of flip-flops = 4.
• Count sequence: $0000$ to $1111$, i.e. 16 distinct states ($0$ to $15$).
• Maximum count = $15$ (then it rolls over to 0).