BE Computer Engineering (Pokhara University) Microprocessor and Assembly Language Programming (PU, CMP 224) Question Paper 2079 Nepal

(a) Internal Architecture of the 8085 (9 marks)

The 8085 is an 8-bit microprocessor with a 16-bit address bus and an 8-bit data bus. Its internal blocks are connected by an internal 8-bit data bus.

Functional block diagram (described): The ALU and the Accumulator + Temporary register feed each other on the left; the Flag register sits beside the ALU; the Register array (B, C, D, E, H, L, SP, PC, and the temporary W, Z registers) connects to the internal bus; the Instruction Register and Decoder drive the Timing & Control Unit, which generates all control signals; the Address buffer (A8–A15) and the Address/Data buffer (AD0–AD7) drive the external buses.

• ALU (Arithmetic and Logic Unit): Performs arithmetic (add, subtract, increment, decrement) and logic (AND, OR, XOR, compare, rotate) operations on 8-bit data. It takes one operand from the accumulator and the other from the temporary register, and the result is normally returned to the accumulator.
• Register array:
  • Accumulator (A): 8-bit register that holds one ALU operand and receives the result; the most-used register.
  • Temporary register: Internal, not accessible to the programmer; holds the second operand for the ALU during an operation.
  • Flag register: 8-bit register with five status flags — S (Sign), Z (Zero), AC (Auxiliary Carry), P (Parity), CY (Carry) — set/reset after ALU operations to record the result's condition.
  • General-purpose registers B, C, D, E, H, L: used singly (8-bit) or as pairs BC, DE, HL (16-bit); HL also acts as a memory pointer.
  • SP (Stack Pointer) and PC (Program Counter) are 16-bit special registers.
• Timing and Control Unit: Generates timing and control signals (RD̄, WR̄, ALE, IO/M̄, status signals, and the clock) that synchronise all internal and external operations. It controls the fetch–decode–execute sequence.
• Instruction Decoder: Receives the opcode from the Instruction Register, decodes it, and tells the control unit which micro-operations (machine cycles, T-states) to generate to execute the instruction.

(b) Hardware Signals (6 marks)

1 mark each for ALE, IO/M̄, READY, HLDA, SID (purpose) and direction collectively.

(a) BIU and EU of the 8086 (9 marks)

The 8086 is internally divided into two concurrent units that share the work of instruction processing.

Bus Interface Unit (BIU):

• Handles all transactions on the external bus: it fetches instructions, reads operands from memory, and writes results to memory/I/O.
• Contains the four segment registers (CS, DS, SS, ES), the Instruction Pointer (IP), the address-generation adder, and the 6-byte instruction queue.
• It computes 20-bit physical addresses by shifting a segment register left by 4 bits and adding the offset.

Execution Unit (EU):

• Decodes and executes instructions taken from the queue.
• Contains the ALU, the general registers (AX, BX, CX, DX), pointer/index registers (SP, BP, SI, DI), and the flag register.
• The EU has no connection to the outside bus; whenever it needs data or an address, it requests the BIU.

Instruction queue and pipelining (fetch–execute overlap): While the EU is busy executing an instruction (which does not require the bus), the BIU uses the otherwise idle bus to pre-fetch up to 6 bytes of the following instructions into the queue. Thus fetching and executing proceed in parallel — a simple two-stage pipeline. This reduces the time the EU waits for instructions and improves throughput. (On a branch/jump the queue is flushed and refilled.)

Block diagram (described): left side = EU with ALU, registers, flags, and EU control; right side = BIU with segment registers, IP, address adder, and the 6-byte queue feeding the EU; the BIU connects to the external address/data bus.

(b) Physical Address Calculation (6 marks)

The 20-bit physical address is formed as:

$$\text{Physical Address} = (\text{Segment} \times 10\text{H}) + \text{Offset}$$

Given CS = 348AH, IP = 4214H:

1. Shift CS left by one hex digit (×10H): $348A\text{H} \times 10\text{H} = 348A0\text{H}$
2. Add the offset IP:

   3 4 8 A 0   H   (segment base)
 +   4 2 1 4   H   (offset)
 -----------
   3 8 A B 4   H

$$\boxed{\text{Physical Address} = 38AB4\text{H}}$$

Why segmentation is used: The 8086 registers are only 16 bits and can address at most 64 KB directly, but the chip has a 20-bit address bus (1 MB). Segmentation lets a 16-bit segment register plus a 16-bit offset together span the full 1 MB space, supports relocatable code/data (only the segment register changes), and gives a logical separation of code, data and stack areas.

(a) Address Map (5 marks)

Requirement: 8 KB EPROM (two 4K×8 chips) from 0000H, then 4 KB RAM (one 4K×8 chip) immediately after.

A 4K block = 4096 = 1000H locations, so each chip spans an address range of size 1000H.

Each 4K chip uses A0–A11 for internal addressing (4096 = 2¹²). The higher lines A12, A13, A14 select the chip; A15 can be tied to the decoder enable.

(b) Interfacing Circuit with 74LS138 (10 marks)

Address lines:

• A0–A11 → connected in parallel to the address inputs of every memory chip.
• A12, A13, A14 → connected to the select inputs C, B, A of the 74LS138 respectively.
• The decoder is enabled in the lower 64 KB by tying G1 = +5 V (high) and Ḡ2A = Ḡ2B = 0 (A15 low, or use A15 on an enable to restrict the range).

Decoder outputs (active-low) select 4K blocks:

Data lines: D0–D7 of the 8085 connect in parallel to the data pins of all three chips (after the AD0–AD7 bus is demultiplexed using ALE and a 74LS373 latch).

Control lines:

• RD̄ → connected to the OĒ (output enable) of both EPROMs and to the RD̄ of the RAM.
• WR̄ → connected to the WĒ (write enable) of the RAM only (EPROM is read-only).
• IO/M̄ is used to qualify the decoder so it responds only to memory accesses — typically IO/M̄ (or its inverse) is fed to one of the decoder enable pins so that the decoder is active only when IO/M̄ = 0 (memory operation).

Circuit (described): 8085 → ALE/74LS373 latch demultiplexes AD0–AD7 into A0–A7; A0–A11 bus to all chips; A12–A14 to 74LS138 C,B,A; IO/M̄ qualifies decoder enable; Ȳ0→EPROM1 CS̄, Ȳ1→EPROM2 CS̄, Ȳ2→RAM CS̄; RD̄→OĒ/RD̄, WR̄→WĒ of RAM; D0–D7 common.

(a) 8085 Program: Largest of 10 unsigned numbers (9 marks)

; Find largest of 10 unsigned 8-bit numbers at 2050H; store at 2060H
        LXI  H, 2050H   ; HL -> start of data block
        MVI  C, 0AH     ; C = count = 10 numbers
        MOV  A, M       ; A = first number (assume it is the largest)
        DCR  C          ; one number already taken, 9 left to compare
        INX  H          ; point to next number
LOOP:   CMP  M          ; compare A with [HL]  (A - M)
        JNC  SKIP       ; if A >= M (no borrow), A is still largest -> skip
        MOV  A, M       ; else M is larger, copy it into A
SKIP:   INX  H          ; advance pointer to next number
        DCR  C          ; decrement count
        JNZ  LOOP       ; repeat until all numbers compared
        STA  2060H      ; store the largest number at 2060H
        HLT             ; stop

Logic: Load the first number into A as the assumed maximum, then compare A with each remaining element. CMP M does A − M without altering A; if a borrow (CY = 1) occurs then M > A, so M is copied into A. After all 10 numbers, A holds the largest, which is stored at 2060H.

(b) Subroutine vs Macro (6 marks)

Advantages of subroutine: saves memory, modular and reusable. Disadvantage: call/return time overhead.

Advantages of macro: faster execution (no overhead), parameters substituted at assembly time. Disadvantage: consumes more memory because the code is duplicated at every call.

Addressing modes of the given 8086 instructions:

(a) MOV AX, 1234H — Immediate addressing. The operand (1234H) is a constant supplied within the instruction itself; it is moved directly into AX. No memory access for the operand.

(b) MOV BX, [SI] — Register indirect addressing. The effective address (EA) = contents of SI; the data segment (DS) supplies the base. The word at physical address (DS×10H + SI) is loaded into BX.

(c) MOV CL, [BX+DI+4] — Based-indexed with displacement addressing. $EA = BX + DI + 4$. The byte at (DS×10H + BX + DI + 4) is loaded into CL.

(d) MOV AX, [2000H] — Direct addressing. The 16-bit offset (2000H) is given directly in the instruction; $EA = 2000\text{H}$, and the word at (DS×10H + 2000H) is loaded into AX.

Five hardware interrupts in order of priority

Highest to lowest:

$$\textbf{TRAP} > \textbf{RST 7.5} > \textbf{RST 6.5} > \textbf{RST 5.5} > \textbf{INTR}$$

Maskable vs Non-maskable

• Maskable interrupts can be enabled or disabled by software using the EI/DI instructions and the SIM instruction (mask bits). RST 7.5, 6.5, 5.5 and INTR are maskable, so the programmer can choose to ignore them.
• Non-maskable interrupt (TRAP) cannot be disabled by any instruction; the CPU will always respond to it.

Why TRAP is special

TRAP has the highest priority and is non-maskable, so it is always serviced. It is triggered by a combination of edge and level, which avoids false triggering due to noise. Because it cannot be disabled, it is reserved for critical conditions such as power failure or other emergency shutdown signals, where the routine must run no matter what.

8255A Control Word (I/O mode, D7 = 1)

The control register format for the I/O (mode-set) configuration is:

Applying the required configuration:

• D7 = 1 → mode-set (active) format
• D6 D5 = 00 → Group A in mode 0
• D4 = 1 → Port A = input
• D3 = 1 → Port C upper = input
• D2 = 0 → Group B in mode 0
• D1 = 0 → Port B = output
• D0 = 0 → Port C lower = output

$$\text{Control word} = 1001\,1000_2 = \boxed{98\text{H}}$$

This value (98H) is written to the 8255A control register to obtain Port A input (mode 0), Port B output (mode 0), Port C upper input, and Port C lower output.

8253/8254 Programmable Interval Timer

The 8253/8254 PIT is a peripheral chip containing three independent 16-bit down-counters (Counter 0, 1, 2), each with its own CLK input, GATE input and OUT output. It is used to generate accurate time delays, square-wave frequencies, rate generation, event counting and interrupt timing under software control, relieving the CPU of timing tasks. Each counter is programmed (mode, count, BCD/binary) via a control word, and counts can be read on the fly (the 8254 adds a read-back command). It supports BCD or binary counting.

Three operating modes

Mode 0 — Interrupt on Terminal Count. OUT goes low when the count is loaded and stays low while counting down; when the count reaches zero, OUT goes high and stays high. Application: generating a single, programmable time delay or an interrupt after a fixed number of clock pulses (event counting).

Mode 2 — Rate Generator. OUT is normally high and produces one low-going pulse every N input clocks (a divide-by-N counter), reloading automatically. Application: generating a periodic real-time clock tick / sampling rate for an ADC.

Mode 3 — Square Wave Generator. Produces a continuous square wave of period N clocks (≈50% duty cycle). Application: generating a baud-rate clock or a buzzer/tone output.

Definitions

• T-state: One subdivision of the operation performed in one clock period of the system clock. It is the smallest unit of processor timing (1/clock frequency).
• Machine cycle: The time required to access one memory location or one I/O device, i.e. to complete one read or write (or opcode-fetch) operation. A machine cycle consists of 3 to 6 T-states.
• Instruction cycle: The total time required to fetch, decode and execute one complete instruction. An instruction cycle is made up of one or more machine cycles (typically 1 to 5).

Hierarchy: Instruction cycle ⊇ Machine cycles ⊇ T-states.

Opcode Fetch Machine Cycle

The opcode fetch is the first machine cycle of every instruction and normally requires 4 T-states (T1–T4); some instructions extend it to 6 T-states.

Timing diagram (described):

• T1: Higher address (A8–A15) is placed on the address bus; the lower byte (A0–A7) appears on AD0–AD7; ALE = 1 to latch the low address. Status (IO/M̄ = 0, S1 = 1, S0 = 1) indicates an opcode fetch.
• T2: ALE goes low; RD̄ = 0 is asserted; memory places the opcode on AD0–AD7; the processor begins reading.
• T3: The opcode is read from the data bus into the instruction register; RD̄ returns high at the end.
• T4: The processor decodes the opcode (no bus activity).

So the opcode fetch machine cycle requires 4 T-states.

8086 Program: read a character and display the next ASCII character

It reads one key, adds 1 to its ASCII code, and prints the resulting character.

.MODEL SMALL
.STACK 100H
.CODE
MAIN PROC
        ; --- Read one character from keyboard (with echo) ---
        MOV  AH, 01H      ; INT 21H fn 01H: read char from STDIN, echo, AL = ASCII
        INT  21H          ; AL = entered character

        ; --- Compute the next character in ASCII sequence ---
        INC  AL           ; AL = next ASCII code
        MOV  DL, AL       ; move it into DL for display

        ; --- Display the next character ---
        MOV  AH, 02H      ; INT 21H fn 02H: display char in DL on STDOUT
        INT  21H

        ; --- Terminate program ---
        MOV  AH, 4CH      ; INT 21H fn 4CH: terminate to DOS
        INT  21H
MAIN ENDP
END  MAIN

INT 21H functions used:

• Function 01H – Read a character from the keyboard with echo; the ASCII code is returned in AL.
• Function 02H – Display the character whose ASCII code is in DL on the console.
• Function 4CH – Terminate the program and return control to DOS.

For example, if the user types A (41H), INC AL gives 42H, so B is displayed.

Memory-mapped I/O vs I/O-mapped I/O (8085)

Summary: Memory-mapped I/O is flexible (full instruction set, large number of ports) but consumes memory address space; I/O-mapped I/O keeps the memory space intact and needs less decoding but is limited to 256 ports and only IN/OUT instructions, distinguished by the IO/M̄ signal.

Assume A = 7FH = 0111 1111B before each instruction (executed independently).

(a) ADI 01H

$7FH + 01H = 80H$, so A = 80H = 1000 0000B.

• CY = 0 (no carry out of bit 7)
• AC = 1 (carry from bit 3 → bit 4, since lower nibble F + 1)
• S = 1 (bit 7 = 1, result negative)
• Z = 0 (result ≠ 0)
• P = 0 (one '1' bit → odd parity)

(b) ANI 0FH

$7FH \text{ AND } 0FH$ = 0000 1111B, so A = 0FH.

• CY = 0 (logical AND always resets carry)
• AC = 1 (on the 8085, ANI/ANA sets AC = 1)
• S = 0 (bit 7 = 0)
• Z = 0 (result ≠ 0)
• P = 1 (four '1' bits → even parity)

(c) RLC (rotate accumulator left)

7FH = 0111 1111B; rotate left by one — the MSB (0) goes to both CY and bit 0: result = 1111 1110B = FEH.

• CY = 0 (old bit 7 = 0 shifted into carry)
• RLC affects only the CY flag; S, Z, P, AC are unchanged.
• A = FEH.

8259A Programmable Interrupt Controller (PIC)

The 8259A PIC is a peripheral chip that manages hardware interrupts for the microprocessor. The 8085 has only one general-purpose interrupt line (INTR), but a system usually has many interrupting devices. The 8259A accepts requests from up to 8 devices (IR0–IR7), prioritises them, decides which to service, and supplies the corresponding interrupt vector/CALL address to the CPU during the interrupt-acknowledge (INTĀ) sequence.

How it expands interrupt-handling capability

• It provides 8 prioritised interrupt inputs through a single INTR line, and up to 64 levels by cascading one master with eight slave 8259As.
• It performs priority resolution (fixed, rotating, etc.) so the highest-priority pending request is serviced first.
• Individual interrupts can be masked via the Interrupt Mask Register (IMR), and lower-priority interrupts can be nested.
• It automatically supplies the vectoring information, removing this burden from the CPU.

Initialization Command Words (ICWs)

Before use, the 8259A is initialised with a sequence of ICWs:

• ICW1: Starts initialisation; specifies edge/level triggering, single or cascaded mode, and whether ICW4 is needed.
• ICW2: Sets the interrupt vector base address (high byte of the vectoring/CALL address) for IR0–IR7.
• ICW3: Used only in cascade mode — on the master it marks which IR lines have slaves; on a slave it gives its slave ID.
• ICW4: Specifies the operating environment — 8086/8088 vs 8085 mode, automatic EOI, buffered mode, and special fully-nested mode.

After ICWs, Operation Command Words (OCWs) control day-to-day operation (masking, EOI, priority rotation).