BE Computer Engineering (Pokhara University) Microprocessor and Assembly Language Programming (PU, CMP 224) Question Paper 2078 Nepal

(a) Internal Architecture of the Intel 8086 (8 marks)

The 8086 is a 16-bit microprocessor whose internal architecture is divided into two independent functional units that operate in parallel.

Functional block diagram (described): The CPU is split vertically into two units sharing the data path internally:

• Execution Unit (EU) — contains: the general-purpose registers AX, BX, CX, DX (each split into high/low bytes), pointer/index registers SP, BP, SI, DI, the 16-bit ALU, the Flag register, and the control circuitry / instruction decoder.
• Bus Interface Unit (BIU) — contains: the four segment registers (CS, DS, SS, ES), the Instruction Pointer (IP), the 6-byte instruction queue, and the address generation adder (Σ) that forms the 20-bit physical address. The BIU drives the external address/data bus.

        BIU                         EU
  +---------------+          +-------------------+
  | CS DS SS ES   |          | AX BX CX DX       |
  | IP            |          | SP BP SI DI       |
  | Σ (addr adder)|          | ALU  Flags        |
  | 6-byte queue  |<-------->| Instr. decoder    |
  +-------+-------+          +-------------------+
          |  (external bus)
   A0-A19 / D0-D15

Role of the BIU: Handles all transactions with memory and I/O — it generates the 20-bit physical address, fetches instruction op-codes, reads operands and writes results, and pre-fetches instruction bytes into the queue.

Role of the EU: Decodes and executes instructions taken from the queue, performs arithmetic/logic in the ALU, updates flags, and computes the effective (offset) address of operands. The EU has no direct connection to the system bus; it requests memory/I/O access through the BIU.

Instruction pipelining (queue): Because fetching and executing are done by two separate units, while the EU is busy executing an instruction the BIU simultaneously pre-fetches up to 6 bytes of the following instructions into the FIFO queue. The EU therefore usually finds the next op-code already inside the chip and need not wait for a memory fetch. This overlap of fetch and execute keeps the bus busy, reduces idle (wait) time, and raises throughput. The queue is flushed only on a branch/jump/call, after which pre-fetching restarts.

(b) 20-bit Physical Address Generation (6 marks)

The 8086 has a 20-bit address bus (1 MB memory) but only 16-bit registers. A physical address is formed from a segment and an offset:

$$\text{Physical Address} = (\text{Segment} \times 10\text{H}) + \text{Offset}$$

The BIU shifts the 16-bit segment value left by 4 bits (i.e. multiplies by 16) and adds the 16-bit offset in the address adder, yielding a 20-bit address.

Computation for CS = 2000H, IP = 1234H:

$$\text{Segment} \times 10\text{H} = 2000\text{H} \times 10\text{H} = 20000\text{H}$$ $$\text{Physical Address} = 20000\text{H} + 1234\text{H} = \mathbf{21234H}$$

So the instruction is fetched from physical address 21234H.

8086 Program: Largest of Ten Unsigned 8-bit Numbers

The array of ten bytes is at offset 2000H in the data segment; the maximum is stored at 3000H.

DATA SEGMENT
    ORG 2000H
    ARRAY DB 10 DUP(?)      ; ten unsigned bytes
    ORG 3000H
    MAX   DB ?             ; result
DATA ENDS

CODE SEGMENT
    ASSUME CS:CODE, DS:DATA
START:
    MOV  AX, DATA          ; load segment base
    MOV  DS, AX            ; initialise DS
    MOV  SI, 2000H         ; SI -> first element (pointer)
    MOV  CX, 0009H         ; loop count = N-1 = 9 comparisons
    MOV  AL, [SI]          ; AL = first element = current max
NEXT:
    INC  SI                ; point to next element
    CMP  AL, [SI]          ; compare current max with next
    JNC  SKIP              ; if AL >= [SI] (no carry) keep AL
    MOV  AL, [SI]          ; else new larger value -> AL
SKIP:
    LOOP NEXT              ; CX = CX-1; repeat until CX = 0
    MOV  [3000H], AL       ; store the largest at offset 3000H
    MOV  AH, 4CH
    INT  21H              ; terminate
CODE ENDS
END START

Explanation of Instructions, Addressing Modes and Registers

• MOV AX,DATA / MOV DS,AX — immediate then register addressing; DS cannot be loaded directly, so the segment base is passed through AX to initialise the data segment.
• MOV SI,2000H — immediate addressing; SI (Source Index) is used as a pointer to walk through the array.
• MOV CX,0009H — immediate; CX is the dedicated loop counter decremented automatically by LOOP. Only 9 comparisons are needed for 10 elements.
• MOV AL,[SI] — register-indirect addressing; the effective address is the contents of SI. AL holds the running maximum.
• INC SI — advances the pointer by one byte to the next element.
• CMP AL,[SI] — register-indirect; performs AL − [SI] and sets flags without changing AL. For unsigned numbers the Carry Flag (CF) indicates the result of the magnitude comparison.
• JNC SKIP — conditional jump: if CF = 0 (AL ≥ [SI]) skip the update; otherwise AL is smaller and must be replaced.
• MOV AL,[SI] — copies the new larger element into AL.
• LOOP NEXT — decrements CX and jumps to NEXT while CX ≠ 0, automating the iteration.
• MOV [3000H],AL — direct addressing; stores the final maximum at offset 3000H.
• INT 21H (AH=4CH) — DOS function to terminate the program.

Note on the comparison: JNC is correct for unsigned data because CF reflects an unsigned borrow; for signed data JGE/JL (using SF and OF) would be used instead.

(a) Interfacing 16 KB EPROM + 16 KB RAM to 8086 (Minimum Mode) (9 marks)

Memory organisation: Because the 8086 has a 16-bit data bus, memory is built as two 8-bit banks — an even (lower) bank enabled by A0 = 0 and an odd (upper) bank enabled by BHE = 0. Each 16 KB block is therefore made of two 8 KB chips (one in each bank). Address line A0 and BHE are not sent to the chips as part of the size decoding; the remaining lines A1–A19 select a word.

Sizing: 16 KB = $2^{14}$ bytes ⇒ needs 14 address bits A0–A13 within each block; per bank each 8K×8 chip needs A1–A13. The higher lines A14–A19 are decoded (e.g. by a 74LS138) to produce the chip-select for each block.

Address map (one convenient assignment):

(EPROM is placed at the top because the 8086 reset vector is FFFF0H; RAM at the bottom for the interrupt vector table at 00000H.)

Decoding logic: A 3-to-8 decoder (74LS138) takes high-order lines A14–A19 with M/IO̅ as an enable; one output (active-low) drives RAM CS̅ and another drives EPROM CS̅. Within each block A1–A13 address the cells, A0 selects the even bank, BHE̅ selects the odd bank, and RD̅/WR̅ drive OE̅/WE̅ of the RAM (EPROM has OE̅ only).

A14..A19 --> 74LS138 --> Y0 = RAM CS  (00000-03FFFH)
  (M/IO=1 enable)        Y7 = EPROM CS (FC000-FFFFFH)
A1..A13  --> chip address lines (both banks)
A0=0  --> even bank EN ;  BHE=0 --> odd bank EN
RD,WR --> OE,WE

(b) Why Two Banks; Function of BHE and A0 (5 marks)

The 8086 has a 16-bit data bus and can transfer either a byte or a word (16 bits) in one bus cycle. To allow a byte to be read from any address while still moving 16 bits in one cycle, memory is split into two 8-bit banks:

• Even bank — even addresses (A0 = 0), connected to data lines D0–D7.
• Odd bank — odd addresses, connected to data lines D8–D15, selected by BHE̅ (Bus High Enable).

Bank selection during transfers:

Thus A0 enables the even bank and BHE̅ enables the odd bank. An aligned word (even address) is fetched in a single cycle; a misaligned word (odd address) needs two cycles, so word data is normally placed at even addresses.

(a) Interrupt Structure of the 8086 (7 marks)

An interrupt is an event that suspends the normal program flow so the CPU can run an Interrupt Service Routine (ISR), then resume. The 8086 supports 256 interrupt types (0–255).

Hardware vs Software interrupts:

Sequence of operations when an interrupt is recognised:

1. The processor completes the current instruction.
2. The flag register is pushed onto the stack.
3. The IF and TF flags are cleared (disables further maskable interrupts and single-step).
4. The current CS is pushed, then the current IP is pushed (so a far return address is saved).
5. The interrupt type number is obtained (from INTR's interrupt-acknowledge cycle, from INT n, or fixed for NMI = type 2).
6. The new IP is loaded from vector address type×4 and the new CS from type×4 + 2.
7. Control transfers to the ISR; it ends with IRET, which pops IP, CS and the flags, restoring the interrupted program.

(b) Interrupt Vector Table and Address for Type 21H (5 marks)

The Interrupt Vector Table (IVT) is a reserved block in the lowest 1 KB of memory (00000H–003FFH). It holds 256 vectors, one per interrupt type. Each vector is 4 bytes: the lower 2 bytes are the ISR offset (IP) and the upper 2 bytes are the ISR segment (CS).

The table location for any type n is:

$$\text{Vector address} = n \times 4$$

For interrupt type 21H:

$$21\text{H} \times 4 = 21\text{H} \times 4 = 84\text{H}$$

So the vector for INT 21H occupies addresses 00084H–00087H:

• IP at 00084H–00085H
• CS at 00086H–00087H

Four Addressing Modes of the 8086

The addressing mode specifies how the operand's effective address (EA) — the 16-bit offset within the segment — is obtained.

1. Register addressing — the operand is in a register; no memory access.

• Example: MOV AX, BX — AX ← BX. No EA computed.

2. Immediate addressing — the operand is a constant in the instruction itself.

• Example: MOV AL, 25H — AL ← 25H. Data is part of the instruction.

3. Direct addressing — the EA (offset) is given explicitly in the instruction.

• Example: MOV AX, [2000H] — EA = 2000H; physical address = DS×10H + 2000H.

4. Register-indirect addressing — the EA is held in a base/index register (BX, SI, DI or BP).

• Example: MOV AX, [SI] — EA = (SI); physical address = DS×10H + SI.

(Other valid choices include:)

5. Based / Indexed addressing — EA = base/index register + displacement.

• Example: MOV AX, [BX+4] — EA = BX + 4.

6. Based-indexed addressing — EA = base + index (+ displacement).

• Example: MOV AX, [BX+SI] — EA = BX + SI.

In all memory modes the physical address = (segment register × 10H) + EA, with the default segment being DS (or SS when BP is used).

8255A Programmable Peripheral Interface (PPI)

The 8255A is a general-purpose programmable I/O chip providing 24 I/O lines in three 8-bit ports.

Internal block diagram (described):

        +------------------------------------+
  D0-D7-| Data Bus Buffer |                  |
        |-----------------|  Group A control |-- PA0-PA7 (Port A)
  RD --|                  |                  |-- PC4-PC7 (Port C upper)
  WR --| Read/Write       |------------------|
  A0 --| Control Logic    |  Group B control |-- PB0-PB7 (Port B)
  A1 --|                  |                  |-- PC0-PC3 (Port C lower)
  CS --|                  |                  |
  RESET|                  |                  |
        +------------------------------------+

It contains a data-bus buffer, read/write control logic (using RD̅, WR̅, A0, A1, CS̅), and two control groups (Group A and Group B) that manage the three ports.

Three ports:

• Port A (PA0–PA7): 8-bit, can be input/output; supports Modes 0, 1, 2.
• Port B (PB0–PB7): 8-bit, input/output; supports Modes 0, 1.
• Port C (PC0–PC7): 8-bit, can be used as two 4-bit ports (upper/lower) for I/O, or as handshake/status lines in Modes 1 and 2.

Control word in Mode 0 (simple I/O): Bit D7 = 1 sets I/O mode. The remaining bits configure direction:

• D6,D5 = Group A mode (00 for Mode 0); D2 = Group B mode (0 for Mode 0).
• D4 = Port A direction (1 = input, 0 = output)
• D3 = Port C upper direction
• D1 = Port B direction
• D0 = Port C lower direction

Example: control word 80H (1000 0000) ⇒ all three ports as outputs in Mode 0. 90H makes Port A input, others output. In Mode 0 there is no handshaking — data is simply latched/buffered, suitable for LEDs, switches and similar devices.

Memory-mapped I/O vs I/O-mapped (Isolated) I/O

Memory-mapped I/O — advantages: any instruction can access ports, so full arithmetic/logic can be performed directly on port data; flexible and powerful. Disadvantages: consumes part of the memory address space (less memory available) and needs full 20-bit decoding (more hardware).

I/O-mapped I/O — advantages: keeps the entire memory space free; needs only 16-bit decoding (simpler, cheaper); the M/IO̅ line clearly separates I/O from memory. Disadvantages: only IN/OUT are available (data must first be brought into the accumulator), giving less flexibility; limited to 64 KB of port addresses.

Instructions: I/O-mapped uses IN AL, port / OUT port, AL (and DX for port addresses > FFH). Memory-mapped uses ordinary instructions such as MOV AL, [port_addr] and MOV [port_addr], AL.

Programmable Interrupt Controller (8259A)

Need: The 8086 has only one maskable interrupt input (INTR) but a real system has many interrupting devices (timer, keyboard, disk, etc.). The 8259A is a dedicated chip that multiplexes up to 8 interrupt requests (IR0–IR7) onto the single INTR line, resolves their priority, and supplies the correct interrupt type number to the CPU during the interrupt-acknowledge cycle. It also lets individual interrupts be masked and reprogrammed without extra logic.

Priority management: Each request enters the Interrupt Request Register (IRR). The Priority Resolver selects the highest-priority pending request, sets the corresponding bit in the In-Service Register (ISR), and asserts INTR. By default IR0 has the highest and IR7 the lowest priority (fixed priority), but it can be programmed for rotating priority (priorities rotate so every device gets fair service) or specific priority. Lower-priority interrupts are held until the current ISR issues an EOI (End Of Interrupt) that clears the ISR bit.

Cascading for more than 8 interrupts: One 8259A acts as the master and up to eight slave 8259As are connected to its IR inputs, giving up to 8 × 8 = 64 interrupt levels. The master and slaves communicate over the three cascade lines (CAS0–CAS2) and the SP̅/EN̅ pin (set to master/slave). When a slave's request wins, the master places that slave's identity on CAS0–CAS2; the addressed slave then drives the interrupt type number onto the data bus during the second INTA̅ pulse. Each chip is initialised by ICW1–ICW4 (and operated via OCW1–OCW3), with ICW3 telling the master which IR lines have slaves and telling each slave its cascade ID.

(a) Function of Four 8086 Instructions (4 marks)

• XCHG — exchanges the contents of two operands (register/register or register/memory).
  • Example: XCHG AX, BX swaps AX and BX.
• LEA — Load Effective Address: loads the offset (effective address) of a memory operand into a register, not its contents.
  • Example: LEA SI, MSG loads the offset of MSG into SI.
• CMP — compares two operands by computing destination − source and setting the flags (ZF, CF, SF, OF) without storing the result.
  • Example: CMP AL, 05H sets ZF if AL = 5, CF if AL < 5 (unsigned).
• LOOP — decrements CX and jumps to the target label while CX ≠ 0; used for counted loops.
  • Example: LOOP NEXT repeats the loop body CX times.

(b) Flags after ADD AL, BL with AL = 7FH, BL = 01H (2 marks)

Compute: $7FH + 01H = 80H$ (binary $0111\,1111 + 0000\,0001 = 1000\,0000$). Result in AL = 80H.

Procedures (Subroutines) in 8086

A procedure is a named, reusable block of code that performs a specific task; it is invoked with CALL and returns with RET. It avoids code duplication and supports modular programming. It is defined between PROC and ENDP directives:

MYPROC PROC NEAR
   ; ... body ...
   RET
MYPROC ENDP

NEAR vs FAR Procedures

How CALL and RET Use the Stack

CALL:

1. The processor first computes the return address (the address of the instruction after CALL).
2. For a NEAR call it pushes IP onto the stack (SP ← SP−2). For a FAR call it pushes CS then IP (SP ← SP−4).
3. It then loads the new IP (and CS for FAR) with the procedure's address and transfers control.

RET:

1. RET pops the saved return address back off the stack — IP for NEAR, IP and CS for FAR — so execution resumes at the instruction following the original CALL.
2. The stack pointer is restored (SP ← SP+2 for NEAR, +4 for FAR). A RET n form additionally adds n to SP to discard parameters that were pushed before the call.

The stack thus guarantees correct nesting: the most recently saved return address is the first one restored (LIFO), allowing procedures to call other procedures safely.

Short Notes (any TWO)

(a) 8253/8254 Programmable Interval Timer

The 8253/8254 is a peripheral chip containing three independent 16-bit down-counters (Counter 0, 1, 2), each with a CLK input, a GATE input and an OUT output, plus a control word register addressed via A0,A1. It is programmed by loading a control word and a count. It is used for generating accurate time delays, baud-rate clocks, square waves and event counting. Six operating modes:

• Mode 0 – Interrupt on terminal count
• Mode 1 – Hardware-retriggerable one-shot
• Mode 2 – Rate generator (divide-by-N)
• Mode 3 – Square-wave generator
• Mode 4 – Software-triggered strobe
• Mode 5 – Hardware-triggered strobe

The 8254 is an enhanced 8253 supporting higher clock rates and a read-back command.

(b) DMA and the 8237 DMA Controller

Direct Memory Access (DMA) transfers data directly between memory and an I/O device without CPU involvement for each byte, giving very high transfer rates (useful for disks, networks). The 8237 is a 4-channel DMA controller. Sequence: the device asserts DREQ → the 8237 raises HRQ (HOLD) to the CPU → the CPU finishes its bus cycle, floats its buses and replies with HLDA → the 8237 takes control of the address/data/control buses, issues DACK to the device, and drives the memory address and read/write strobes to move a block of data → on completion it releases HOLD and the CPU resumes. The 8237 supports single, block and demand transfer modes.

(c) Minimum vs Maximum Mode of the 8086

The 8086's MN/MX̅ pin selects the operating mode: