BE Computer Engineering (Pokhara University) Electronics Devices and Circuits (PU, ELX 120) Question Paper 2079 Nepal

(a) Intrinsic vs Extrinsic Semiconductors; N-type and P-type Formation

Intrinsic vs Extrinsic

In an intrinsic semiconductor the number of free electrons equals the number of holes, $n = p = n_i$ (intrinsic carrier concentration), and conduction is small.

N-type formation: A pure tetravalent semiconductor (Si) is doped with a pentavalent (donor) impurity such as P, As or Sb. Four valence electrons form covalent bonds, while the fifth electron is loosely bound and becomes a free electron at room temperature.

• Majority carriers: electrons; Minority carriers: holes.
• Donor level lies just below the conduction band, so $n \approx N_D$.

P-type formation: Si is doped with a trivalent (acceptor) impurity such as B, Al, Ga or In. Only three covalent bonds are completed, leaving a vacancy (hole) that accepts an electron from a neighbouring bond.

• Majority carriers: holes; Minority carriers: electrons.
• Acceptor level lies just above the valence band, so $p \approx N_A$.

In both cases the crystal remains electrically neutral, and the mass-action law $np = n_i^2$ holds.

(b) Depletion Region and Effect of Bias

Formation (unbiased): When P and N regions are joined, free electrons from the N-side diffuse to the P-side and holes from the P-side diffuse to the N-side, recombining near the junction. This leaves immobile ionised donors (+) on the N-side and acceptors (−) on the P-side, creating a region depleted of mobile carriers — the depletion region. The resulting internal electric field sets up a barrier potential $V_0$ (≈0.7 V for Si, ≈0.3 V for Ge) that opposes further diffusion, establishing equilibrium.

Energy-band picture: the bands bend so that the Fermi level is constant across the junction; the conduction/valence bands of the P-side are raised by $qV_0$ relative to the N-side.

Forward bias (P to +, N to −): The external field opposes the barrier field.

• Barrier potential decreases to $(V_0 - V)$.
• Depletion width narrows.
• Bands bend back, majority carriers cross easily → large current flows.

Reverse bias (P to −, N to +): The external field aids the barrier field.

• Barrier potential increases to $(V_0 + V)$.
• Depletion width widens.
• Only a small reverse saturation current (minority carriers) flows.

Circuit: battery + series resistor across the diode; forward bias has P terminal to the positive terminal, reverse bias reverses the battery.

(a) Full-Wave Bridge Rectifier — Operation

Circuit: Four diodes (D1–D4) arranged in a bridge across the transformer secondary; the load $R_L$ connects across the bridge output. No centre-tapped transformer is required.

Positive half-cycle: A is positive, B negative. Diodes D1 and D2 conduct (forward biased), D3 and D4 are off. Current flows A → D1 → $R_L$ → D2 → B.

Negative half-cycle: B is positive, A negative. Diodes D3 and D4 conduct, D1 and D2 are off. Current flows B → D3 → $R_L$ → D4 → A — in the same direction through $R_L$.

Thus both half-cycles produce a unidirectional output.

Waveforms: Input is a full sine wave; output is a series of positive half-sine humps (pulsating DC) at twice the input frequency. In each half-cycle two diodes are in series, so the peak output is $V_{m(out)} = V_m - 2V_\gamma$.

(b) Numerical

Given $V_m = 24$ V (secondary peak), $V_\gamma = 0.7$ V (two diodes conduct).

Peak across load: $V_{m(out)} = 24 - 2(0.7) = 22.6\ \text{V}$

DC output voltage:

$$V_{dc} = \frac{2V_{m(out)}}{\pi} = \frac{2(22.6)}{\pi} = 14.39\ \text{V}$$

RMS output: $V_{rms} = \dfrac{V_{m(out)}}{\sqrt2} = \dfrac{22.6}{1.414} = 15.98\ \text{V}$

Ripple factor:

$$r = \sqrt{\left(\frac{V_{rms}}{V_{dc}}\right)^2 - 1} = \sqrt{\left(\frac{15.98}{14.39}\right)^2 - 1} = 0.482 \approx 0.48$$

(Theoretical ideal value for full-wave = 0.482.)

Rectifier efficiency:

$$\eta = \frac{8}{\pi^2} \times 100\% = 81.2\%$$

Shunt capacitor filter: A capacitor placed across $R_L$ charges to the peak during conduction and discharges slowly through $R_L$ between peaks, filling in the valleys of the output. This greatly reduces the AC (ripple) component. The ripple factor becomes

$$r = \frac{1}{4\sqrt3\, f C R_L}$$

so increasing $C$ (or $R_L$) lowers the ripple, giving a smoother, more nearly constant DC output.

(a) Voltage-Divider (Self) Bias

Circuit: For an NPN BJT, $R_1$ connects $V_{CC}$ to the base, $R_2$ connects base to ground (forming a divider that fixes the base voltage), $R_C$ is in the collector lead and $R_E$ in the emitter lead.

Why most stable: The divider $R_1$–$R_2$ holds the base voltage $V_B$ nearly constant, independent of $\beta$. The emitter resistor $R_E$ provides negative (current-series) feedback: if $I_C$ tends to rise (due to temperature or a $\beta$ change), the emitter voltage $V_E = I_E R_E$ rises, reducing $V_{BE} = V_B - V_E$, which reduces $I_B$ and hence brings $I_C$ back down. Because $I_C \approx (V_B - V_{BE})/R_E$ is essentially independent of $\beta$, the Q-point is far more stable than fixed bias (where $I_B = (V_{CC}-V_{BE})/R_B$ depends directly on $V_{CC}$ and $I_C = \beta I_B$ depends strongly on $\beta$).

(b) Operating-Point Calculation

Given $V_{CC}=12$ V, $R_1=47$ kΩ, $R_2=10$ kΩ, $R_C=2.2$ kΩ, $R_E=1$ kΩ, $\beta=100$, $V_{BE}=0.7$ V.

Thevenin base voltage:

$$V_{TH}=V_{CC}\frac{R_2}{R_1+R_2}=12\times\frac{10}{57}=2.105\ \text{V}$$

Thevenin resistance:

$$R_{TH}=R_1\parallel R_2=\frac{47\times10}{57}=8.246\ \text{k}\Omega$$

Emitter / collector current:

$$I_E=\frac{V_{TH}-V_{BE}}{R_E+\frac{R_{TH}}{\beta+1}}=\frac{2.105-0.7}{1000+\frac{8246}{101}}=\frac{1.405}{1081.6}=1.30\ \text{mA}$$ $$I_C\approx I_E = 1.30\ \text{mA}$$

(If $R_{TH}/(\beta+1)$ is neglected: $I_C\approx1.405/1000 = 1.40$ mA.)

Collector-emitter voltage:

$$V_{CE}=V_{CC}-I_C(R_C+R_E)=12-1.30\times10^{-3}(2200+1000)=12-4.16=7.84\ \text{V}$$

Q-point: $I_C \approx 1.30$ mA, $V_{CE} \approx 7.84$ V.

DC Load Line: Plot $I_C$ vs $V_{CE}$.

• Cut-off (x-intercept): $V_{CE}=V_{CC}=12$ V.
• Saturation (y-intercept): $I_{C(sat)}=\dfrac{V_{CC}}{R_C+R_E}=\dfrac{12}{3200}=3.75$ mA. Draw the line joining (12 V, 0) and (0, 3.75 mA); the Q-point sits on it at (7.84 V, 1.30 mA), near mid-line giving good swing.

(a) Ideal Op-Amp Parameters

• Input offset voltage ($V_{io}$): The small differential DC voltage that must be applied between the two inputs to make the output exactly zero. Ideally 0 V.
• CMRR (Common-Mode Rejection Ratio): Ratio of differential gain to common-mode gain, $\text{CMRR}=\left|\dfrac{A_d}{A_{cm}}\right|$, usually in dB ($20\log$). It measures how well the op-amp rejects signals common to both inputs. Ideally infinite.
• Slew rate (SR): Maximum rate of change of output voltage, $SR=\left.\dfrac{dV_o}{dt}\right|_{max}$ (V/µs). It limits the largest undistorted output at high frequency. Ideally infinite.
• Gain–bandwidth product (GBW): The product of open-loop gain and bandwidth, constant for a given op-amp; equals the unity-gain frequency $f_T$. Ideally infinite.

(b) Inverting Amplifier — Gain Derivation

Circuit: Input signal $V_i$ through $R_1$ to the inverting (−) input; feedback resistor $R_f$ from output to (−) input; the (+) input grounded.

For an ideal op-amp: infinite input impedance ($I_-=0$) and virtual short, so the (−) node is a virtual ground ($V_-=V_+=0$).

KCL at the inverting node:

$$\frac{V_i-0}{R_1}=\frac{0-V_o}{R_f}$$ $$\boxed{A_v=\frac{V_o}{V_i}=-\frac{R_f}{R_1}}$$

The minus sign shows a 180° phase inversion.

(c) Summing Amplifier Design: $V_o = -(2V_1 + 5V_2)$

For a summing inverter, $V_o=-\left(\dfrac{R_f}{R_1}V_1+\dfrac{R_f}{R_2}V_2\right)$.

Require $\dfrac{R_f}{R_1}=2$ and $\dfrac{R_f}{R_2}=5$.

Choose $R_f = 10\ \text{k}\Omega$:

• $R_1=\dfrac{R_f}{2}=5\ \text{k}\Omega$
• $R_2=\dfrac{R_f}{5}=2\ \text{k}\Omega$

Circuit: $V_1$ through $R_1=5$ kΩ and $V_2$ through $R_2=2$ kΩ both join the inverting node; $R_f=10$ kΩ feedback; non-inverting input grounded (a bias resistor $R_1\parallel R_2\parallel R_f \approx 1.25$ kΩ may be added at the + input). Check: $V_o=-(\frac{10}{5}V_1+\frac{10}{2}V_2)=-(2V_1+5V_2)$. ✓

Zener Diode as a Voltage Regulator

A Zener diode is operated in reverse breakdown. In this region a large change in current produces almost no change in voltage, so it clamps its terminal voltage at $V_Z$.

Circuit: Unregulated DC input $V_{in}$ → series resistor $R_s$ → node, with the Zener connected in reverse across the load $R_L$ (cathode to +). $R_s$ drops the excess voltage and limits the Zener current.

The output is held at $V_o = V_Z$. Current relations:

$$I_s=\frac{V_{in}-V_Z}{R_s},\qquad I_Z=I_s-I_L$$

Line regulation (input varies, $R_L$ fixed): If $V_{in}$ rises, $I_s$ and hence $I_Z$ rise; the extra current flows through the Zener while $V_Z$ stays nearly constant, so $V_o$ holds steady. The change appears across $R_s$.

Load regulation (load varies, $V_{in}$ fixed): If $I_L$ increases, $I_Z$ decreases by the same amount (and vice-versa) so that $I_s$ stays roughly constant; $V_o = V_Z$ is maintained.

Conditions for regulation:

• The Zener must stay in breakdown: $V_{in} > V_Z$ and $I_Z \ge I_{Z(min)}$ (knee current).
• $I_Z$ must not exceed $I_{Z(max)}=P_{Z(max)}/V_Z$.
• Hence $R_s$ is chosen so that $I_{Z(min)} \le I_Z \le I_{Z(max)}$ over the full range of $V_{in}$ and $I_L$.

N-Channel JFET — Construction and Working

Construction: A bar of N-type semiconductor forms the channel, with ohmic contacts at the two ends called the Drain (D) and Source (S). Two heavily doped P-type regions are diffused on opposite sides and joined together as the Gate (G). The gate–channel junctions form PN diodes.

Working principle: The JFET is a majority-carrier, voltage-controlled device.

• With $V_{DS}$ applied (D positive) and $V_{GS}=0$, electrons flow from S to D giving drain current $I_D$.
• The gate is reverse biased ($V_{GS}$ negative). This widens the depletion regions of the gate junctions into the channel, narrowing the conducting channel and reducing $I_D$.
• As $V_{GS}$ is made more negative, the channel narrows further; the gate voltage thus controls $I_D$ with virtually no gate current (very high input impedance).

Pinch-off voltage ($V_P$): The value of $V_{DS}$ (with $V_{GS}=0$) at which the depletion regions almost touch and the channel is 'pinched off', so that $I_D$ becomes nearly constant (enters saturation). Equivalently, $V_P$ is the gate voltage $V_{GS(off)}$ that reduces $I_D$ to zero.

Drain–source saturation current ($I_{DSS}$): The maximum drain current that flows in saturation when $V_{GS}=0$ and $V_{DS}\ge|V_P|$. It is the reference current in Shockley's equation:

$$I_D=I_{DSS}\left(1-\frac{V_{GS}}{V_P}\right)^2$$

Depletion-type vs Enhancement-type MOSFET

Transfer characteristics (N-channel):

• D-MOSFET: Curve passes through $I_D=I_{DSS}$ at $V_{GS}=0$; $I_D$ increases for positive $V_{GS}$ (enhancement) and decreases to zero at $V_{GS}=V_P$ (negative). The curve exists on both sides of the $I_D$ axis.
• E-MOSFET: $I_D=0$ until $V_{GS}$ exceeds the positive threshold $V_T$; beyond $V_T$, $I_D$ rises as a parabola. The curve exists only for $V_{GS}>V_T$.

Application: The enhancement MOSFET is preferred in digital logic / CMOS switching circuits (and as a power switch), because it is normally OFF at $V_{GS}=0$ and turns ON only when driven — ideal for low static power consumption.

Comparison of BJT Amplifier Configurations

Key points / uses:

• CE has both high voltage and current gain → highest power gain; the general-purpose amplifier. Output is inverted.
• CB has voltage gain but $A_i<1$; low input/high output impedance → used at high (RF) frequencies and for impedance step-up.
• CC has voltage gain ≈1 but high current gain; high input/low output impedance → used as a buffer / impedance matcher (emitter follower).

(a) Barkhausen Criterion

For sustained (steady) oscillations in a feedback oscillator, two conditions on the loop must be met:

1. Loop gain magnitude: $|A\beta| = 1$ (the product of amplifier gain $A$ and feedback factor $\beta$ equals unity). For oscillations to start, $|A\beta| > 1$.
2. Loop phase: The total phase shift around the loop is $0°$ (or $360°$), i.e. feedback is positive (regenerative).

(b) RC Phase-Shift Oscillator (BJT)

Circuit: A single-stage CE amplifier (BJT with $R_1$–$R_2$ bias, $R_C$, $R_E$–$C_E$) whose output is fed back to the input through a three-section RC ladder network (three identical $R$–$C$ stages).

Phase shift: The CE amplifier itself provides 180° of phase shift (inverting). To satisfy Barkhausen ($360°$ total), the RC network must provide the remaining 180°. Each RC section gives up to 60°, so three sections together give the required 180° at one specific frequency. This makes the total loop phase shift $180°+180°=360°=0°$, so positive feedback is obtained only at that frequency, and the circuit oscillates there.

Frequency of oscillation:

$$f=\frac{1}{2\pi RC\sqrt{6}}$$

(For a transistor version, with $R_C$ loading, $f=\dfrac{1}{2\pi RC\sqrt{6+4(R_C/R)}}$.) The amplifier must supply a gain of at least 29 to overcome the network attenuation.

Wien-Bridge Oscillator

Circuit: An op-amp (or two-stage BJT) non-inverting amplifier with two feedback paths:

• Positive feedback through a Wien (lead–lag) RC network: a series $R$–$C$ in series with a parallel $R$–$C$, connected to the (+) input.
• Negative feedback through a resistive divider $R_1$–$R_2$ (often with a lamp/diode for amplitude stabilisation) to the (−) input.

Working: The lead–lag network has zero phase shift at one frequency $f_0$ and there passes a maximum fraction (1/3) of the output to the + input. Since the amplifier is non-inverting (0° shift), the total loop phase is 0° only at $f_0$, satisfying Barkhausen. To start and sustain oscillation, the amplifier gain must make $A\beta \ge 1$; because $\beta = 1/3$ at $f_0$, the minimum gain is 3, i.e. $1+R_2/R_1 = 3 \Rightarrow R_2 = 2R_1$.

Frequency:

$$f_0=\frac{1}{2\pi RC}$$

Calculation with $R=10\ \text{k}\Omega$, $C=0.01\ \mu\text{F}=0.01\times10^{-6}$ F:

$$f_0=\frac{1}{2\pi(10\times10^{3})(0.01\times10^{-6})}=\frac{1}{2\pi\times10^{-4}}=1591\ \text{Hz}\approx1.59\ \text{kHz}$$

Minimum amplifier gain = 3.

Op-Amp Integrator

Circuit: Input $V_i$ through resistor $R$ to the inverting (−) input; a capacitor $C$ as the feedback element from output to the (−) input; non-inverting input grounded. The (−) node is a virtual ground.

Operation / Derivation: With an ideal op-amp the input current equals the capacitor current ($I_- = 0$, virtual ground $V_-=0$):

$$\frac{V_i}{R}=-C\frac{dV_o}{dt}$$

Integrating:

$$\boxed{V_o=-\frac{1}{RC}\int V_i\,dt + V_o(0)}$$

The output is the (inverted, scaled) time-integral of the input — e.g. a square-wave input gives a triangular-wave output.

Why a feedback resistor $R_f$ is added in parallel with $C$: For DC (and the op-amp's input offset voltage/bias current), the capacitor acts as an open circuit, so the integrator has infinite DC gain. Any small DC offset is integrated continuously and drives the output into saturation (drift). Connecting a resistor $R_f$ across $C$ provides a DC feedback path, limiting the low-frequency/DC gain to $-R_f/R$ and preventing saturation. $R_f$ is chosen large enough that the circuit still integrates correctly above the frequency $f \approx 1/(2\pi R_f C)$.

Drift and Diffusion Currents; Einstein Relation

Drift current: The current produced when an electric field $E$ is applied to a semiconductor. Carriers acquire a drift velocity $v_d=\mu E$ ($\mu$ = mobility), giving:

$$J_{drift}=q(n\mu_n+p\mu_p)E=\sigma E$$

Electrons and holes drift in opposite directions but contribute current in the same direction.

Diffusion current: The current that flows because of a concentration gradient of carriers (independent of any field). Carriers move from a high-concentration region to a low-concentration region:

$$J_{n,diff}=qD_n\frac{dn}{dx},\qquad J_{p,diff}=-qD_p\frac{dp}{dx}$$

where $D_n, D_p$ are the diffusion constants. This mechanism is responsible for current in PN junctions.

Einstein Relationship: At thermal equilibrium the diffusion constant and mobility of a carrier are related by

$$\frac{D}{\mu}=\frac{kT}{q}=V_T$$

so $D_n=\mu_n V_T$ and $D_p=\mu_p V_T$, where $V_T=kT/q\approx 26$ mV at 300 K. It states that the same scattering that limits mobility also governs diffusion, linking the two transport mechanisms through the thermal voltage. A larger mobility implies a proportionally larger diffusion constant.

Positive Clipper and Positive Clamper

Positive Clipper

Circuit: A diode in series with the load (or shunt across output) arranged so it conducts on the positive half. In the common shunt clipper, the input goes through a series resistor $R$; a diode is connected from output to ground with its anode toward the output (no bias for clipping at 0 V; a battery $V_R$ in series with the diode sets the clipping level).

Operation: When the input rises above the reference (e.g. $+V_R+V_\gamma$), the diode conducts and holds the output at that level — the positive peaks are 'clipped' (removed); the negative half passes unchanged.

Transfer characteristic: A straight line $V_o=V_i$ for $V_i$ below the clip level, then a flat horizontal segment clamped at the reference level for higher inputs.

Application: Wave-shaping / amplitude limiting — protecting a circuit input from excessive positive voltage, or squaring sine waves.

Positive Clamper

Circuit: A capacitor in series with the input, and a diode in shunt at the output. For a positive clamper the diode conducts on the negative half-cycle, charging the capacitor to $V_m$ (with the polarity that adds to the input).

Operation: The capacitor charges to the peak input voltage on the first negative half and then acts as a DC battery in series with the input, shifting the entire waveform upward so its negative peak sits at ≈0 V (or at $+V_R$ if a bias is used). The shape and peak-to-peak value are unchanged; only the DC level (clamp) is added.

Transfer characteristic: A 45° line $V_o=V_i+V_{DC}$ — the same waveform offset by the added DC level.

Application: DC restoration — e.g. restoring the DC reference (black level) in video/TV signals after AC coupling.