BE Computer Engineering (Pokhara University) Electronics Devices and Circuits (PU, ELX 120) Question Paper 2078 Nepal

(a) Intrinsic vs Extrinsic Semiconductors

n-type formation: A pentavalent (donor) impurity such as phosphorus, arsenic or antimony is added. Four of its five valence electrons form covalent bonds; the fifth is loosely bound and becomes a free electron. Each donor atom donates one electron.

• Majority carriers: electrons
• Minority carriers: holes

p-type formation: A trivalent (acceptor) impurity such as boron, gallium or indium is added. It has only three valence electrons, leaving a vacancy (hole) in one bond. Each acceptor accepts an electron, creating a hole.

• Majority carriers: holes
• Minority carriers: electrons

(b) Drift and Diffusion Current

Drift current: current produced when charge carriers move under the influence of an applied electric field. $J_{drift} = q(n\mu_n + p\mu_p)E$.

Diffusion current: current produced when carriers move from a region of high concentration to low concentration due to a concentration gradient. $J_{diff,n} = qD_n\dfrac{dn}{dx}$.

Carrier concentrations: Since $N_D = 5\times10^{16}\gg n_i$, the electron concentration equals the donor concentration:

$$n \approx N_D = 5\times10^{16}\ \text{/cm}^3$$

Using mass-action law $np = n_i^2$:

$$p = \frac{n_i^2}{n} = \frac{(1.5\times10^{10})^2}{5\times10^{16}} = \frac{2.25\times10^{20}}{5\times10^{16}} = 4.5\times10^{3}\ \text{/cm}^3$$

Effect of temperature on intrinsic conductivity: As temperature rises, more covalent bonds break, increasing $n_i$ exponentially ($n_i^2 \propto T^3 e^{-E_g/kT}$). The rapid rise in carrier concentration dominates over the slight fall in mobility, so the conductivity of an intrinsic semiconductor increases with temperature (negative temperature coefficient of resistance).

(a) Need for Biasing and Voltage-Divider Bias

Biasing fixes the DC operating point (Q-point) of a BJT so that the transistor stays in the active region throughout the input signal swing. Without proper biasing the output would be clipped/distorted and amplification would not be faithful.

Voltage-divider (self) bias circuit: $R_1$ and $R_2$ form a divider across $V_{CC}$ that fixes the base voltage; $R_C$ is in the collector and $R_E$ in the emitter provides feedback stabilisation.

      +Vcc
       |
   +---+---+
  R1       Rc
   |        |
   +---B   C
   |    \  /
  R2     [Q]  ---> Vout
   |    /  \
   |   E    
   |   |
   |   Re
   |   |
  GND-GND

Why it is stable: The base voltage $V_B \approx V_{CC}R_2/(R_1+R_2)$ is set by the resistor divider and is nearly independent of $\beta$. The emitter resistor $R_E$ provides negative feedback: if $I_C$ rises (due to temperature or higher $\beta$), $V_E = I_E R_E$ rises, reducing $V_{BE} = V_B - V_E$, which reduces $I_B$ and brings $I_C$ back down. Because $I_C \approx (V_B - V_{BE})/R_E$ is almost independent of $\beta$, the Q-point is far more stable than fixed bias, where $I_C = \beta I_B$ depends directly on $\beta$.

(b) Q-point Calculation

Thevenin equivalent of the base divider:

$$V_{TH} = V_{CC}\frac{R_2}{R_1+R_2} = 12\times\frac{10}{50} = 2.4\ \text{V}$$ $$R_{TH} = R_1\,\|\,R_2 = \frac{40\times10}{50} = 8\ \text{k}\Omega$$

Base loop ($V_{BE}=0.7$ V):

$$I_B = \frac{V_{TH}-V_{BE}}{R_{TH}+(\beta+1)R_E} = \frac{2.4-0.7}{8\text{k}+101\times1\text{k}} = \frac{1.7}{109\text{k}} = 15.6\ \mu\text{A}$$ $$I_{CQ} = \beta I_B = 100\times15.6\ \mu\text{A} \approx 1.56\ \text{mA}$$ $$V_{CEQ} = V_{CC} - I_C(R_C+R_E) = 12 - 1.56\text{m}\times3\text{k} = 12 - 4.68 \approx 7.32\ \text{V}$$

Comment: Saturation $I_{C(sat)} = V_{CC}/(R_C+R_E) = 12/3\text{k} = 4\ \text{mA}$ and cutoff $V_{CE}=12$ V. With $V_{CEQ}=7.32$ V and $I_{CQ}=1.56$ mA, the Q-point lies near the centre of the DC load line, allowing a good symmetrical output swing.

(a) Ideal Operational Amplifier

An ideal op-amp is a differential-input, single-ended-output high-gain DC amplifier whose output is $V_o = A(V_+ - V_-)$ with $A\to\infty$.

Ideal characteristics:

• Infinite open-loop gain ($A_{OL}\to\infty$)
• Infinite input impedance ($Z_{in}\to\infty$, zero input current)
• Zero output impedance ($Z_{out}=0$)
• Infinite bandwidth
• Infinite CMRR
• Zero input offset voltage; output = 0 when both inputs are equal

Practical terms:

• Input offset voltage ($V_{IO}$): the small differential DC voltage that must be applied between the inputs to make the output exactly zero; it arises from mismatch in the input stage.
• CMRR (Common-Mode Rejection Ratio): the ratio of differential gain to common-mode gain, $\text{CMRR}=20\log_{10}(A_d/A_{cm})$ dB; a high CMRR means the op-amp strongly rejects signals common to both inputs (noise, hum).
• Slew rate (SR): the maximum rate of change of output voltage, $SR=\left|\dfrac{dV_o}{dt}\right|_{max}$ in V/µs; it limits the largest undistorted output amplitude at high frequency.

(b) Inverting Summing Amplifier

Three inputs $V_1,V_2,V_3$ connect through $R_1,R_2,R_3$ to the inverting node; the non-inverting input is grounded; feedback resistor $R_f$.

The inverting node is a virtual ground ($V_-\approx0$). KCL at that node (no current into the op-amp):

$$\frac{V_1}{R_1}+\frac{V_2}{R_2}+\frac{V_3}{R_3} = -\frac{V_o}{R_f}$$ $$\boxed{V_o = -\left(\frac{R_f}{R_1}V_1+\frac{R_f}{R_2}V_2+\frac{R_f}{R_3}V_3\right)}$$

Design for $V_o = -(2V_1+5V_2+V_3)$: choose $R_f = 10\ \text{k}\Omega$, then

• $R_f/R_1 = 2 \Rightarrow R_1 = 5\ \text{k}\Omega$
• $R_f/R_2 = 5 \Rightarrow R_2 = 2\ \text{k}\Omega$
• $R_f/R_3 = 1 \Rightarrow R_3 = 10\ \text{k}\Omega$

These three inputs through $5\,\text{k},2\,\text{k},10\,\text{k}$ into the inverting node with $R_f=10\,\text{k}$ produce the required weighted sum.

(a) Barkhausen Criterion

For sustained (steady-amplitude) oscillations in a feedback amplifier with gain $A$ and feedback factor $\beta$, the loop gain must satisfy:

1. Magnitude condition: $|A\beta| = 1$
2. Phase condition: total phase shift around the loop $= 0^\circ$ (or $360^\circ$), i.e. the feedback is positive (regenerative).

An oscillator needs no external input because, at switch-on, electrical noise/transients contain a small component at the oscillation frequency. With positive feedback and loop gain $\ge 1$ at that frequency, this component is fed back in phase and amplified repeatedly until it builds up into a sustained oscillation; amplitude is then limited by circuit non-linearity so that effective $|A\beta|=1$.

(b) BJT RC Phase-Shift Oscillator

Circuit: A common-emitter BJT amplifier (which gives $180^\circ$ phase shift) is followed by a three-section RC ladder feedback network. Each RC section provides about $60^\circ$, so three sections give the additional $180^\circ$, making the total loop phase $360^\circ$ and satisfying the phase condition.

Frequency of oscillation: For the three identical RC sections (including the loading effect of the amplifier input resistance $R$),

$$f = \frac{1}{2\pi RC\sqrt{6+4k}}\quad\text{where } k = R_C/R$$

For the idealised case the standard result is:

$$\boxed{f = \frac{1}{2\pi RC\sqrt{6}}}$$

Minimum gain: For the RC phase-shift network the feedback attenuation is $1/29$, so the amplifier must provide a gain of at least

$$\boxed{|A| \ge 29}$$

to satisfy $|A\beta|=1$.

Formation of the Depletion Region

When p-type and n-type materials are joined, the high concentration of free electrons on the n-side and holes on the p-side causes diffusion across the junction. Electrons crossing into the p-side recombine with holes, and holes crossing into the n-side recombine with electrons. This leaves behind immobile ionised donor atoms (positive) on the n-side and acceptor atoms (negative) on the p-side. This region near the junction, swept free of mobile carriers, is the depletion region.

The exposed ions set up an internal electric field and a barrier potential ($\approx0.7$ V for Si, $0.3$ V for Ge) that opposes further diffusion. At equilibrium the drift current due to this field exactly balances the diffusion current, so no net current flows.

V-I Characteristic of a Silicon Diode

Forward bias (p positive, n negative): The applied voltage opposes the barrier potential. Below the cut-in (knee) voltage $V_\gamma \approx 0.7$ V the current is very small; beyond it the depletion region narrows and current rises sharply (approximately exponentially) following the diode equation $I = I_S\left(e^{V/\eta V_T}-1\right)$.

Reverse bias (p negative, n positive): The barrier widens; only a tiny reverse saturation current $I_S$ (due to minority carriers) flows, nearly constant with voltage. Beyond the reverse breakdown voltage the current increases abruptly (avalanche/Zener breakdown).

Curve description (I on y-axis, V on x-axis):

• First quadrant: flat near zero up to ~0.7 V, then a steep upward knee.
• Third quadrant: a small constant reverse current, then a sharp downward drop at the breakdown voltage $-V_{BR}$.

(a) Full-Wave Bridge Rectifier

Circuit: Four diodes ($D_1$–$D_4$) form a bridge; the AC transformer secondary connects to one diagonal and the load $R_L$ to the other.

Operation:

• During the positive half-cycle, $D_1$ and $D_2$ conduct, passing current through $R_L$ in a fixed direction.
• During the negative half-cycle, $D_3$ and $D_4$ conduct, again passing current through $R_L$ in the same direction.

Thus both half-cycles produce a unidirectional output. The output frequency is twice the input ($2f$). PIV of each diode $= V_m$.

Waveforms: Input is a full sine wave; output is a series of positive half-sine humps (both halves rectified), one hump per input half-cycle.

(b) Ripple Calculation

Given $V_p = 20$ V, $C = 470\,\mu\text{F}$, $R_L = 1\ \text{k}\Omega$, $f = 50$ Hz (full-wave $\Rightarrow$ ripple frequency $2f = 100$ Hz).

Load current: $I_L \approx V_p/R_L = 20/1000 = 20\ \text{mA}$.

Peak-to-peak ripple voltage:

$$V_{r(pp)} = \frac{I_L}{2fC} = \frac{0.02}{100\times470\times10^{-6}} = \frac{0.02}{0.047} \approx 0.426\ \text{V}$$

RMS ripple (triangular): $V_{r(rms)} = \dfrac{V_{r(pp)}}{2\sqrt3} = \dfrac{0.426}{3.464} \approx 0.123\ \text{V}$

DC output: $V_{dc} \approx V_p - \dfrac{V_{r(pp)}}{2} = 20 - 0.213 \approx 19.79\ \text{V}$

Ripple factor:

$$r = \frac{V_{r(rms)}}{V_{dc}} = \frac{0.123}{19.79} \approx 0.0062 \;(\approx 0.62\%)$$

n-Channel JFET

Construction: A bar of n-type silicon forms the channel; ohmic contacts at its ends are the Drain (D) and Source (S). Two heavily doped p-type regions diffused on opposite sides are joined together to form the Gate (G). The two p-n junctions are reverse-biased in operation.

Principle of operation: The JFET is a voltage-controlled device. With $V_{DS}>0$, electrons flow from source to drain through the channel. A reverse gate voltage ($V_{GS}<0$) widens the depletion regions of the gate junctions, narrowing the conducting channel and reducing the drain current $I_D$. Thus $V_{GS}$ controls $I_D$ with essentially zero gate current (very high input impedance).

Pinch-off voltage ($V_P$): the value of $V_{DS}$ (with $V_{GS}=0$) at which the depletion regions just meet and the channel is "pinched off," after which $I_D$ becomes nearly constant (saturates) at $I_{DSS}$. Equivalently it is the negative $V_{GS}$ that reduces $I_D$ to zero.

Drain (Output) Characteristics — $I_D$ vs $V_{DS}$

For each fixed $V_{GS}$ the curve shows three regions:

• Ohmic (linear) region: for small $V_{DS}<|V_P|$, the channel acts like a voltage-controlled resistor; $I_D$ rises almost linearly with $V_{DS}$.
• Saturation (pinch-off / active) region: for $V_{DS}>|V_P|$, $I_D$ stays nearly constant (set by $V_{GS}$); this region is used for amplification. $I_D = I_{DSS}\left(1-\dfrac{V_{GS}}{V_P}\right)^2$.
• Breakdown region: at very high $V_{DS}$ the gate-drain junction breaks down and $I_D$ rises sharply (avoided in normal operation).

Enhancement-Type n-Channel MOSFET (E-MOSFET)

Structure: Two heavily doped n+ regions (source and drain) are diffused into a p-type substrate. A thin layer of $SiO_2$ insulates the metal gate from the substrate. There is no physically diffused channel between source and drain in the enhancement type.

Operation: With $V_{GS}=0$ no channel exists, so $I_D\approx0$. When a positive $V_{GS}$ greater than the threshold voltage $V_T$ is applied, the gate field repels holes and attracts electrons to the surface beneath the oxide, inducing (enhancing) an n-type inversion layer that connects source and drain. Increasing $V_{GS}$ above $V_T$ widens this channel and increases $I_D$:

$$I_D = k\,(V_{GS}-V_T)^2\quad\text{for } V_{GS}>V_T$$

Threshold voltage ($V_T$): the minimum gate-to-source voltage required to induce the conducting inversion channel and turn the device on.

Difference in Transfer Characteristic ($I_D$ vs $V_{GS}$)

The enhancement device operates only in enhancement mode, whereas the depletion type can work in both depletion and enhancement modes.

Comparison of BJT Amplifier Configurations

Practical Applications

• CE: general-purpose audio/voltage amplifier (most common, high power gain).
• CB: high-frequency (RF) amplifier, since it has low input capacitance and good high-frequency response.
• CC (emitter follower): impedance matching / buffer stage between a high-impedance source and a low-impedance load.

(a) Op-Amp Integrator

Circuit: Inverting configuration with an input resistor $R$ from $V_{in}$ to the inverting node and a feedback capacitor $C$ from output to the inverting node; non-inverting input grounded.

Derivation: The inverting input is a virtual ground ($V_-=0$). The input current equals the capacitor current (no current into the op-amp):

$$\frac{V_{in}}{R} = -C\frac{dV_o}{dt}$$

Integrating:

$$\boxed{V_o(t) = -\frac{1}{RC}\int_0^t V_{in}\,dt + V_o(0)}$$

The output is the (scaled, inverted) time integral of the input.

(b) Square-Wave Input

For a square wave (constant positive then constant negative levels), the integral of each constant level is a ramp. Therefore the output is a triangular wave:

• During the positive input level the output ramps down (negative slope, because of inversion).
• During the negative input level the output ramps up.

Limitation of a practical integrator: at DC and very low frequencies the capacitor's reactance is very high, so the op-amp's input offset/bias current is integrated and the output drifts and saturates. A large feedback resistor $R_f$ is placed across $C$ to provide a DC path and limit the low-frequency gain.

Zener Diode as a Voltage Regulator

Circuit: The Zener diode is connected in reverse bias across the load $R_L$, with a series resistor $R_S$ between the unregulated supply $V_{in}$ and the Zener/load node.

Operation: When operated in its breakdown region, the Zener maintains an almost constant voltage $V_Z$ across itself (and hence across the load) despite changes in input voltage or load current. The series resistor $R_S$ absorbs the excess voltage and limits the current. If $V_{in}$ rises, the extra current flows through the Zener (not the load); if the load current rises, the Zener current falls — in both cases the load voltage stays at $V_Z$.

Calculation

Given $V_Z=6.2$ V, $V_{in}=12$ V, $R_S=470\,\Omega$, $I_L=8$ mA, $R_Z\approx0$.

Current through series resistor:

$$I_S = \frac{V_{in}-V_Z}{R_S} = \frac{12-6.2}{470} = \frac{5.8}{470} \approx 12.34\ \text{mA}$$

Zener current (KCL, $I_S = I_Z + I_L$):

$$I_Z = I_S - I_L = 12.34 - 8 = 4.34\ \text{mA}$$

Power dissipated in the Zener:

$$P_Z = V_Z I_Z = 6.2 \times 4.34\ \text{mA} \approx 26.9\ \text{mW}$$

(a) Hartley Oscillator

An LC feedback oscillator using a tapped inductor (two inductances $L_1$ and $L_2$, or a centre-tapped coil with mutual inductance $M$) and a single capacitor $C$ in the tank circuit. The tap provides the $180^\circ$ feedback phase needed with a CE amplifier. Frequency of oscillation:

$$f = \frac{1}{2\pi\sqrt{(L_1+L_2+2M)\,C}}$$

Gain condition: $A \ge L_1/L_2$ (or $L_2/L_1$). Used in RF signal generators and radio receivers.

(b) Wien-Bridge Oscillator

An RC oscillator using a Wien bridge network: a series RC and a parallel RC form the frequency-selective positive-feedback path, while $R_1,R_2$ form the negative-feedback (gain-setting) arm with an op-amp. At the balance frequency the network gives zero phase shift, so a non-inverting amplifier ($0^\circ$) satisfies the phase condition. Frequency:

$$f = \frac{1}{2\pi RC}$$

The amplifier must provide a gain of exactly 3 ($R_f/R_1 = 2$) to sustain oscillation. Produces a low-distortion sine wave in the audio range.

(c) Crystal Oscillator and Frequency Stability

Uses a piezoelectric quartz crystal as the resonant element. The crystal behaves as a very high-Q ($\sim10^4$–$10^6$) electrical equivalent of a series RLC in parallel with a shunt capacitance, giving two close resonances: series resonance $f_s$ and parallel resonance $f_p$. Because the crystal's mechanical resonance is extremely stable and its $Q$ is very high, the oscillation frequency is almost independent of temperature, supply and load changes, giving excellent frequency stability (parts per million). Used as clocks in microprocessors, watches and communication systems.