BE Computer Engineering (IOE, TU) Microprocessor (IOE, EX 551) Question Paper 2079 Nepal

(a) Internal architecture of the 8086 [10]

The 8086 is internally divided into two independent functional units that work in parallel:

Bus Interface Unit (BIU) — handles all communication with the outside world over the system bus. It contains:

• The four segment registers (CS, DS, SS, ES) and the Instruction Pointer (IP).
• The address-generation/adder circuit that forms the 20-bit physical address (segment × 16 + offset).
• The 6-byte instruction queue (pre-fetch queue).
• The bus-control logic.

The BIU fetches instructions, reads operands from memory/ports and writes results back, i.e. it performs all memory and I/O transfers.

Execution Unit (EU) — actually executes the instructions. It contains:

• The general-purpose registers AX, BX, CX, DX, SP, BP, SI, DI.
• The ALU (16-bit) and the flag register.
• The control unit / instruction decoder that decodes the instruction taken from the queue and issues control signals.

The EU has no direct connection to the system bus; whenever it needs data from memory it asks the BIU to fetch it.

(Block diagram, described in words: a vertical split — left side the EU with ALU, registers, flags, decoder; right side the BIU with segment registers, IP, address adder and the 6-byte queue; both joined by an internal data bus.)

Pipelining (fetch–execute overlap): While the EU is busy executing the current instruction, the BIU uses the idle bus cycles to pre-fetch the next instructions and fill the 6-byte queue. Thus instruction fetch and instruction execute overlap in time. This:

• Keeps the bus busy almost continuously (better bus utilisation).
• Removes most of the time the EU would otherwise wait for the next opcode, so the effective execution speed and throughput increase.

The queue is flushed only on a branch/jump/call/interrupt (because the pre-fetched bytes are no longer the correct next instructions).

(b) 20-bit physical address generation [6]

Memory is segmented. A segment register holds the upper 16 bits of a 64 KB segment's base; the offset (here IP) gives the displacement inside that segment. The BIU appends four zero bits (multiply by 16) to the segment value and adds the offset:

$$\text{Physical Address} = (\text{Segment} \times 10\text{h}) + \text{Offset}$$

Calculation for CS = 1A2Bh, IP = 003Ch:

$$1A2B\text{h} \times 10\text{h} = 1A2B0\text{h}$$ $$1A2B0\text{h} + 003C\text{h} = \mathbf{1A2EC\text{h}}$$

Physical address = 1A2ECh.

8086 program: largest of ten 8-bit unsigned numbers

The array of ten bytes starts at offset 2000h in the data segment; the result (maximum) is stored at 3000h.

Algorithm: Assume the first element is the largest, then scan the remaining nine elements, replacing the maximum whenever a larger value is found (unsigned comparison using JBE/JA).

        DATA  SEGMENT
        ORG   2000H
        ARR   DB  12H,45H,07H,9AH,33H,80H,21H,FFH,55H,0AH
        ORG   3000H
        RES   DB  ?
        DATA  ENDS

        CODE  SEGMENT
        ASSUME CS:CODE, DS:DATA
        START: MOV  AX, DATA
               MOV  DS, AX
               MOV  SI, 2000H     ; SI -> first element
               MOV  CX, 0009H     ; 9 comparisons remaining
               MOV  AL, [SI]      ; AL = first element (current max)
        NEXT:  INC  SI            ; point to next element
               CMP  AL, [SI]      ; compare current max with element
               JAE  SKIP          ; if AL >= element, keep AL (unsigned)
               MOV  AL, [SI]      ; else element is larger -> new max
        SKIP:  LOOP NEXT          ; CX--, repeat until CX = 0
               MOV  DI, 3000H
               MOV  [DI], AL      ; store result
               MOV  AH, 4CH
               INT  21H           ; terminate
        CODE  ENDS
               END START

Working: AL holds the running maximum. SI walks through the array using register-indirect addressing [SI]. CX is the loop counter; LOOP decrements it and branches while non-zero. Unsigned compare CMP + JAE ensures the larger of two unsigned bytes is retained. After nine comparisons AL contains the largest value, stored to 3000h.

Addressing modes used:

(a) Memory-mapped I/O vs I/O-mapped (isolated) I/O [6]

(b) Interfacing 8 KB EPROM + 4 KB RAM to 8086 [6]

• 8 KB needs $2^{13}$ → 13 address lines (A0–A12).
• 4 KB needs $2^{12}$ → 12 address lines (A0–A11).

The 8086 has a 16-bit data bus, so memory is organised as two banks. For simplicity assume a byte-wide map. Place EPROM at the top of memory (reset vector FFFF0h must lie in ROM) and RAM at the bottom.

Address assignment

Decoding logic (described):

• EPROM: enabled when A19–A13 are all 1. Use a NAND/decoder: CS̅(EPROM) = NOT(A19·A18·A17·A16·A15·A14·A13). Lower lines A12–A0 go to the EPROM address pins.
• RAM: enabled when A19–A12 are all 0. CS̅(RAM) = A19+A18+...+A12 (i.e. NOR of the high lines, active low). Lines A11–A0 address the RAM.
• A 3-to-8 decoder (74LS138) fed by the high address lines, with M/IO̅ as an enable, conveniently generates both chip-select signals; RD̅/WR̅ go to OE̅/WE̅ of the chips.

(Block diagram in words: A0–A12 → address pins; high lines A13–A19 → 74LS138 / NAND gates → CS̅ to EPROM and RAM; RD̅, WR̅ → OE̅, WE̅.)

(a) Interrupt structure of the 8086 [6]

An interrupt suspends the current program, transfers control to an Interrupt Service Routine (ISR), and returns afterwards. The 8086 supports 256 interrupt types (0–255).

Hardware interrupts — caused by external signals on pins:

• NMI (Non-Maskable Interrupt): edge-triggered, cannot be disabled, always type 2.
• INTR (Interrupt Request): maskable by the IF flag (CLI/STI); the device supplies the type number.

Software interrupts — caused by the INT n instruction within the program (e.g. INT 21h); also predefined types like type 0 (divide error), type 1 (single-step), type 3 (breakpoint INT 3), type 4 (INTO overflow).

Response to an INTR request:

1. INTR is sampled at the end of each instruction; if IF = 1, it is recognised.
2. The CPU issues two INTA̅ (interrupt-acknowledge) bus cycles.
3. On the second INTA̅, the interrupting device places the 8-bit interrupt type number on the data bus.
4. The CPU pushes Flags, CS and IP onto the stack, then clears IF and TF.
5. It computes the vector address ($type \times 4$), loads the new IP and CS from the vector table, and begins the ISR. IRET restores IP, CS and Flags.

(b) Interrupt Vector Table (IVT) [4]

The IVT is a table of 256 entries holding the starting address (CS:IP) of every ISR. It occupies the lowest 1 KB of memory, 00000h–003FFh. Each entry is 4 bytes (2 for IP/offset, 2 for CS/segment).

Obtaining the ISR address from the type number $n$:

$$\text{Vector address} = n \times 4$$

The CPU reads the new IP from n×4 and n×4 + 1, and the new CS from n×4 + 2 and n×4 + 3. For example, type 5 → address 5×4 = 14h: IP from 0014h–0015h, CS from 0016h–0017h.

8255 Programmable Peripheral Interface (PPI)

The 8255 is a 40-pin general-purpose programmable parallel I/O device providing 24 I/O lines in three 8-bit ports.

Internal block diagram (described):

• Data bus buffer — 8-bit tristate buffer connecting D0–D7 to the system data bus.
• Read/Write control logic — uses RD̅, WR̅, CS̅, A0, A1, RESET to select Port A / B / C / control register.
• Group A control — controls Port A (PA0–7) and upper half of Port C (PC4–7).
• Group B control — controls Port B (PB0–7) and lower half of Port C (PC0–3).

A1A0 selects: 00→Port A, 01→Port B, 10→Port C, 11→Control register.

Operating modes:

• Mode 0 — Simple I/O: Ports A, B and the two halves of C act as plain input or output latches; no handshaking. Used for simple parallel I/O.
• Mode 1 — Strobed I/O: Ports A and B do handshaked I/O using some Port-C lines as control/status signals (STB̅, IBF, INTR for input; OBF̅, ACK̅, INTR for output).
• Mode 2 — Strobed Bidirectional I/O: Only Port A transfers data both ways over the same 8 lines using 5 Port-C handshake lines. Port B may still work in Mode 0 or 1.

Control word for Port A = input, Port B = output, both Mode 0:

Control word format (D7=1 for I/O mode set):

$$\text{Control word} = 1\,00\,1\,0\,0\,0\,0_2 = 90\text{h}$$

So MOV AL, 90H ; OUT control_reg, AL configures Port A as input and Port B as output in Mode 0.

8086 addressing modes

(a) Immediate addressing — the operand (a constant) is part of the instruction itself.

MOV AX, 1234H   ; load immediate 1234h into AX

(b) Register indirect addressing — the offset of the operand is held in a base/index register (BX, BP, SI or DI); the effective address points into memory. (Default segment DS, except BP→SS.)

MOV AX, [BX]    ; AX <- contents of memory at DS:[BX]

Effective address $= [BX]$.

(c) Based-indexed addressing — the effective address is the sum of a base register (BX/BP) and an index register (SI/DI).

MOV AX, [BX][SI]   ; or MOV AX, [BX+SI]

Effective address $= [BX] + [SI]$. Useful for two-dimensional arrays.

(d) Register relative addressing — the effective address is a register (BX/BP/SI/DI) plus a signed 8/16-bit displacement given in the instruction.

MOV AX, [SI+05H]   ; or MOV AX, 5[SI]

Effective address $= [SI] + 05h$. Convenient for indexing into a record/array element.

Direct Memory Access (DMA)

DMA is a data-transfer technique in which an external DMA controller moves blocks of data directly between memory and an I/O device without involving the CPU for each byte. The CPU is freed during the transfer.

Transfer using HOLD / HLDA (with the 8237):

1. The I/O device asserts a DREQ to the 8237 requesting a transfer.
2. The 8237 raises the HOLD signal to the 8086's HOLD pin, asking the CPU to release the system bus.
3. The CPU finishes the current bus cycle, floats (tri-states) its address, data and control buses, and acknowledges by asserting HLDA.
4. On receiving HLDA, the 8237 becomes bus master. It drives the address bus, issues the memory and I/O read/write signals, and sends DACK to the device.
5. Data is transferred directly between the I/O device and memory, the 8237 incrementing the address and decrementing the byte count each cycle.
6. When the block is complete (terminal count) the 8237 drops HOLD; the CPU then deactivates HLDA and resumes normal operation as bus master.

Two advantages of DMA over program-controlled transfer:

1. Much faster — no instruction fetch/execute overhead per byte; transfer occurs at near bus speed.
2. Frees the CPU to do other work (or stay idle), improving overall system throughput; ideal for high-speed devices like disks.

8253 / 8254 Programmable Interval Timer

The 8253/8254 contains three independent 16-bit down-counters (Counter 0, 1, 2), each with a CLK input, a GATE control input and an OUT output. Each can be programmed for binary or BCD counting and for one of six modes. The 8254 is the higher-speed version of the 8253 with an additional read-back command. It is used for timing, baud-rate generation, real-time clocks, event counting, etc.

Two operating modes:

• Mode 0 — Interrupt on Terminal Count: OUT goes low when the count is loaded and stays low while counting down; it goes high when the count reaches zero, signalling the end of the interval (used as an event interrupt).
• Mode 3 — Square Wave Generator: the counter generates a continuous square wave whose period equals the loaded count. OUT is high for the first half of the count and low for the second half, reloading automatically. Used for clock/baud-rate generation.

Control word for Counter 0, Mode 3, binary, 16-bit (LSB then MSB):

Control word bits: SC1 SC0 | RW1 RW0 | M2 M1 M0 | BCD

$$\text{Control word} = 00\,11\,011\,0_2 = 36\text{h}$$

So MOV AL, 36H ; OUT control_port, AL selects Counter 0 in Mode 3, read/write LSB then MSB, binary count.

Minimum mode vs Maximum mode of the 8086

Role of the MN/MX̅ pin: This single hardware pin selects the operating mode. MN/MX̅ = 1 → minimum mode; MN/MX̅ = 0 → maximum mode. Depending on its level, pins 24–31 of the 8086 take on either their minimum-mode (direct control) meaning or their maximum-mode (status) meaning.

Why the 8288 is needed in maximum mode: In maximum mode the 8086 no longer outputs the memory/I/O control signals directly — instead it outputs the status codes S2̅, S1̅, S0̅ that encode the type of bus cycle. The 8288 Bus Controller decodes these status lines and generates the proper command and control signals (MRDC̅, MWTC̅, IORC̅, IOWC̅, ALE, DEN, DT/R̅, INTA̅, etc.). This off-loads control generation to a dedicated chip and provides the higher drive capability and bus arbitration needed in multiprocessor systems sharing a common bus.

8086 instructions

(a) AAM — ASCII Adjust after Multiply: Used after multiplying two unpacked BCD digits. It divides AL by 10; the quotient goes to AH, the remainder to AL, giving the result as two unpacked BCD digits. Affects SF, ZF, PF (according to AL); AF, CF, OF undefined.

MOV AL, 5 : MUL BL (BL=7) -> AX=0023H ; AAM -> AH=03, AL=05 (35 decimal)

(b) XLAT — Translate: Replaces AL with the byte at DS:[BX + AL]. BX points to a lookup table and AL is the index, so $AL \leftarrow [BX + AL]$. Used for code conversion (e.g. ASCII↔7-segment). No flags affected.

(c) LOOP label — Loop: Decrements CX by 1, then jumps to label if CX ≠ 0; otherwise falls through. Provides a count-controlled loop. It changes CX only; no flags are affected. (Range = short jump, −128 to +127.)

(d) CMPS (CMPSB/CMPSW) — Compare Strings: Compares the byte/word at DS:[SI] with that at ES:[DI] (computes [SI] − [DI] without storing), then updates SI and DI by 1 (byte) or 2 (word) — incremented if DF = 0, decremented if DF = 1. Affects all status flags (CF, ZF, SF, OF, PF, AF). Usually prefixed with REPE/REPNE for block compares.

8086 Flag register

The 8086 has a 16-bit flag register containing 9 active flags: six status (conditional) flags — CF, PF, AF, ZF, SF, OF — that record the result of arithmetic/logic operations, and three control flags — TF, IF, DF — that control processor operation. The remaining bits are unused.

Requested flags:

• Auxiliary Carry flag (AF): Set when there is a carry/borrow out of bit 3 into bit 4 (the low nibble). It is used only for BCD arithmetic by the adjust instructions (AAA, DAA).

• Overflow flag (OF): Set when the result of a signed operation is too large to fit in the destination (sign overflow), i.e. the carry into the sign bit differs from the carry out of it. Indicates a signed-arithmetic error.

• Direction flag (DF): A control flag for string instructions. DF = 0 → auto-increment SI/DI (process low→high addresses); DF = 1 → auto-decrement. Set/cleared by STD/CLD.

• Trap flag (TF): A control flag for debugging. When TF = 1, the processor enters single-step mode, generating a type-1 interrupt after every instruction, allowing a debugger to examine the program step by step.