BE Computer Engineering (IOE, TU) Microprocessor (IOE, EX 551) Question Paper 2078 Nepal

(a) Internal Architecture of the 8085 [7]

The 8085 is an 8-bit microprocessor with a 16-bit address bus (64 KB memory) and an 8-bit data bus (lower address lines AD0–AD7 are multiplexed with data). Its functional blocks are:

Functional block diagram (described in words): The 8-bit internal data bus connects the ALU, the register array, the instruction register/decoder and the timing & control unit. The accumulator and temporary register feed the ALU; the address/data buffers connect the internal bus to the external AD0–AD7 and A8–A15 lines.

• ALU (Arithmetic and Logic Unit): Performs arithmetic ($+,-$, increment, decrement) and logic (AND, OR, XOR, complement, rotate) operations on 8-bit data. One operand comes from the accumulator (A), the other from the temporary register. The result goes back to the accumulator and the five condition flags (S, Z, AC, P, CY) are updated.
• Register array: Six 8-bit general-purpose registers B, C, D, E, H, L (usable as pairs BC, DE, HL), plus the special-purpose accumulator (A) and flag register. The temporary register holds the second ALU operand and is not user-accessible. The W and Z registers are internal temporary registers used by the control unit to hold the operand/address bytes during execution of instructions such as CALL, XCHG and LDA (also not programmer-visible). The Stack Pointer (SP, 16-bit) and Program Counter (PC, 16-bit) are address registers.
• Instruction Register and Decoder: When an opcode is fetched it is latched into the 8-bit instruction register (IR). The decoder decodes the opcode and the encoder/machine-cycle controller generates the sequence of control states for that instruction.
• Timing and Control Unit: Driven by the on-chip clock (X1, X2), it generates all internal timing and the external control signals ALE, RD, WR, IO/M, S0, S1, READY, HOLD/HLDA, RESET that synchronise the CPU with memory and I/O.

(b) 8086 Pipelining and Physical Address [5]

The 8086 is divided into two independent units that work in parallel:

• Bus Interface Unit (BIU): Handles all bus accesses — it fetches instruction bytes from memory and places them in a 6-byte instruction queue (prefetch queue), reads/writes data operands, and computes physical addresses.
• Execution Unit (EU): Takes instruction bytes from the queue, decodes and executes them using the ALU and general registers.

Instruction prefetching: While the EU executes the current instruction (and is not using the bus), the BIU uses the otherwise-idle bus cycles to fetch the next instructions into the queue. This overlap of fetch and execute (a 2-stage pipeline) keeps the bus busy and reduces the time the EU waits for the next opcode, increasing throughput. The queue is flushed on a branch/jump.

Physical address computation: Memory is segmented. The physical (20-bit) address is formed by shifting the 16-bit segment register left by 4 bits and adding the 16-bit offset:

$$\text{Physical Address} = (\text{Segment} \times 16) + \text{Offset} = (\text{Segment} << 4) + \text{Offset}$$

Example: If CS = 2000H and IP = 0050H, then

$$PA = 2000\text{H} \times 10\text{H} + 0050\text{H} = 20000\text{H} + 0050\text{H} = 20050\text{H}.$$

(a) 8085 Program — Largest of 10 unsigned bytes [7]

Data block: 10 bytes from 2050H. Result stored at 2060H.

        LXI  H, 2050H   ; HL -> start of data block
        MVI  C, 0AH     ; C = count = 10
        MOV  A, M       ; A = first number (assume it is the largest)
        DCR  C          ; one number already taken, 9 comparisons left
LOOP:   INX  H          ; point to next number
        CMP  M          ; compare A with [HL]; CY=1 if A < M
        JNC  SKIP       ; if A >= M, A is still largest -> skip
        MOV  A, M       ; else update A with the larger value
SKIP:   DCR  C          ; decrement count
        JNZ  LOOP       ; repeat until all numbers checked
        STA  2060H      ; store the largest number at 2060H
        HLT             ; stop

The accumulator always holds the current maximum; CMP M sets the carry flag when A < M, and only then is A replaced.

(b) CMP B vs SUB B vs CMC [5]

Key difference: CMP B and SUB B perform the same subtraction and affect the same flags, but CMP discards the result (used for comparison/branching) while SUB keeps it in A. CMC is a flag-only instruction that simply toggles the carry bit and does not touch any data register or any other flag.

(a) Memory Interfacing: 4 KB EPROM + 2 KB RAM [8]

Capacities and address ranges

• 4 KB EPROM $= 4096 = 2^{12}$ locations $\Rightarrow$ needs 12 address lines (A0–A11). Starting at 0000H: range 0000H – 0FFFH.
• 2 KB RAM $= 2048 = 2^{11}$ locations $\Rightarrow$ needs 11 address lines (A0–A10). Starting at 8000H: range 8000H – 87FFH.

Memory map

Address/data demultiplexing (ALE): The 8085 multiplexes AD0–AD7. An external octal latch (74LS373) latches AD0–AD7 on the falling edge of ALE to produce the stable lower address A0–A7; A8–A15 come directly from the CPU. The latched A0–A11 (EPROM) / A0–A10 (RAM) go to the chip address pins, and AD0–AD7 (after ALE) carry data.

Address decoding logic: Use the high-order lines to generate chip-select ($\overline{CS}$):

• EPROM is selected for 0000H–0FFFH where A15..A12 = 0000. Decode: $\overline{CS}_{EPROM} = A15 + A14 + A13 + A12$ (active-low select using a NOR of the high lines).
• RAM is selected for 8000H–87FFH where A15=1, A14=A13=A12=0 and A11=0. Decode the block with a 3-to-8 decoder (74LS138) fed by A15,A14,A13 (or by A15..A11) so that exactly one output goes low for the RAM block.
• $\overline{RD}$ enables EPROM output; $\overline{RD}/\overline{WR}$ with IO/M = 0 control RAM. IO/M = 0 qualifies all memory accesses.

(b) Memory-mapped vs I/O-mapped (isolated) I/O [4]

Summary: Memory-mapped I/O treats ports like memory locations (flexible, more instructions, but consumes memory address space), whereas isolated I/O keeps a dedicated I/O space accessed only by IN/OUT and distinguished by the IO/M line.

(a) 8255A Internal Block Diagram and Ports [6]

Block diagram (in words): The 8-bit bidirectional data bus buffer connects D0–D7 to the internal bus. The read/write control logic receives $\overline{RD}, \overline{WR}, \overline{CS}, A0, A1$ and routes data to the addressed port or control register. Internally there are two control groups — Group A (controls Port A and Port C-upper) and Group B (controls Port B and Port C-lower) — each driven by the control word in the control register.

• Port A: 8-bit data port; can be programmed in Mode 0, 1 or 2 (it is the only port that supports Mode 2, bidirectional).
• Port B: 8-bit data port; can be programmed in Mode 0 or Mode 1.
• Port C: 8-bit port that can be split into two 4-bit halves (C-upper PC7–PC4 with Group A, C-lower PC3–PC0 with Group B). In Mode 0 it acts as simple I/O; in Modes 1/2 its bits provide handshake/status signals (STB, IBF, INTR, OBF, ACK).
• Group control logic: Decodes the control word and configures each group's mode and direction; it also enables the bit set/reset (BSR) feature for individual Port C bits.

Port addressing (A1 A0): 00 = Port A, 01 = Port B, 10 = Port C, 11 = Control register.

(b) Control Word for the given configuration [6]

Required: Mode 0; Port A = output, Port C-upper = output, Port B = input, Port C-lower = input.

Control word format (D7 = 1 for I/O mode):

Bits: 1 0 0 0 0 0 1 1 $= \mathbf{83H}$.

Initialisation procedure:

        MVI  A, 83H     ; control word
        OUT  CR_ADDR    ; write to 8255 control register (A1A0 = 11)
        ; now Port A & C-upper are outputs, Port B & C-lower are inputs

Write 83H to the control-register address; the device is then ready. Data is sent with OUT to Port A / C-upper and read with IN from Port B / C-lower.

Mode 1 vs Mode 2:

• Mode 1 (strobed I/O): Ports A and B do handshaked input or output; Port C bits supply the handshake signals (STB, IBF, INTR for input; OBF, ACK, INTR for output). Direction is fixed (in or out) per port.
• Mode 2 (strobed bidirectional I/O): Only Port A supports it; Port A transfers data in both directions over the same 8 lines using five Port C bits for handshaking. Mode 2 is the most flexible but is limited to Port A.

Addressing Modes of the 8085

The 8085 has five addressing modes:

1. Immediate addressing — the operand is given in the instruction itself.
   • Example: MVI A, 32H (load 32H into A); LXI H, 2050H. Operand location: within the instruction (next byte/bytes).
2. Register (direct register) addressing — operands are in CPU registers.
   • Example: MOV A, B (copy B into A); ADD C. Operand location: internal registers.
3. Direct addressing — the 16-bit memory address of the operand is specified in the instruction.
   • Example: LDA 2050H (load A from memory 2050H); STA 2060H. Operand location: memory at the address given in the instruction.
4. Register indirect addressing — the address of the operand is held in a register pair (usually HL).
   • Example: MOV A, M (A ← memory pointed to by HL); ADD M. Operand location: memory at the address contained in HL.
5. Implied / implicit addressing — the operand is implied by the opcode; no address/register is specified.
   • Example: CMA (complement A); RAL, STC. Operand location: implied (usually the accumulator/flags).

Hardware Interrupts of the 8085

The 8085 has five hardware interrupt pins. Their properties:

The vector address is computed as $\text{RST}\,n \times 8$, e.g. RST 6.5 $\to 6.5 \times 8 = 52 = 34\text{H}$.

SIM and RIM

• SIM (Set Interrupt Mask): Uses the accumulator to set/reset the masks of RST 7.5, 6.5, 5.5. Bits D0–D2 are the mask bits (1 = masked), D3 = MSE (Mask Set Enable — must be 1 for the masks to take effect), and D4 = R7.5 resets the RST 7.5 edge-triggered flip-flop. SIM is also used to output SOD (serial output data) via bits D6 (SDE) and D7. SIM cannot affect TRAP.
• RIM (Read Interrupt Mask): Reads the current mask status of RST 7.5/6.5/5.5 into the accumulator (D0–D2 = masks, D3 = IE interrupt-enable, D4–D6 = pending interrupts), and reads the SID serial input on D7.

The EI (enable) and DI (disable) instructions globally enable/disable all maskable interrupts; TRAP is unaffected by EI/DI/SIM.

8253 Programmable Interval Timer — Operating Modes

The 8253 has three independent 16-bit counters, each programmable in six modes (Mode 0–Mode 5):

• Mode 0 – Interrupt on Terminal Count
• Mode 1 – Hardware Retriggerable One-shot
• Mode 2 – Rate Generator (divide-by-N)
• Mode 3 – Square Wave Generator
• Mode 4 – Software Triggered Strobe
• Mode 5 – Hardware Triggered Strobe

Mode 0 — Interrupt on Terminal Count

After the count is loaded, the output goes low. The counter decrements on each clock pulse; when it reaches zero (terminal count), the output goes high and remains high. The rising edge is typically used as an interrupt signal. Loading a new count or a low GATE pauses/restarts counting. It is a one-shot count-down used to generate a delay/interrupt after a programmed number of clocks.

Mode 3 — Square Wave Generator

The output is a square wave with period equal to the loaded count $N$. For an even count, the output is high for $N/2$ clocks and low for $N/2$ clocks; for an odd count it is high one extra clock. The counter automatically reloads, so the square wave is continuous. Output frequency $= f_{clk}/N$. Commonly used to generate baud-rate or system clock frequencies.

Mode (Control) Word Format

Written to the control-register address; format (D7…D0):

Example: Counter 0, read/load LSB then MSB, Mode 3, binary $\Rightarrow$ 00 11 011 0 = 36H.

Direct Memory Access (DMA)

DMA is a data-transfer technique in which an external DMA controller transfers data directly between an I/O device and memory without the CPU executing instructions for each byte. The CPU is temporarily disconnected from the buses so the controller can drive them.

DMA transfer using HOLD and HLDA

1. The I/O device requests a transfer; the DMA controller activates the HOLD input of the 8085.
2. At the end of the current machine cycle, the 8085 completes the bus cycle, floats (tri-states) its address, data and control buses, and acknowledges by asserting HLDA (Hold Acknowledge).
3. The DMA controller now becomes bus master: it places the memory address, asserts the read/write control signals, and transfers data directly between memory and the I/O device (one byte per bus cycle, or a block in burst mode).
4. When the transfer is complete, the controller removes HOLD; the 8085 deactivates HLDA, regains the buses, and resumes normal program execution.

Advantage over programmed I/O

In programmed I/O the CPU must execute several instructions (poll status, read/write, update pointer, loop) for every byte, which is slow and keeps the CPU fully occupied. DMA transfers data at near bus speed without CPU instruction overhead, so it is much faster and frees the CPU to do other work (it is only paused while the buses are borrowed).

(a) Stack and PUSH/POP [3]

The stack is a LIFO (last-in first-out) region of read/write memory used to store data and return addresses temporarily. The Stack Pointer (SP), a 16-bit register, always points to the top of the stack; in the 8085 the stack grows downward (towards lower addresses).

• PUSH rp (e.g. PUSH B): SP is decremented, the high-order register (B) is stored, SP is decremented again, the low-order register (C) is stored. Net effect: $SP \leftarrow SP - 2$ and the 16-bit pair is saved.
• POP rp (e.g. POP B): the low-order byte (C) is read from $[SP]$, SP is incremented, the high-order byte (B) is read, SP is incremented again. Net effect: $SP \leftarrow SP + 2$ and the pair is restored.

PUSH/POP must be balanced so the stack pointer is restored before RET.

(b) CALL/RET vs RST n [3]

• CALL addr16 / RET: CALL is a 3-byte instruction that pushes the return address (current PC) onto the stack and jumps to any 16-bit address given in the instruction. RET pops the return address from the stack back into PC. CALL can target the entire 64 KB space and may be conditional (CZ, CNZ, …).
• RST n: RST n is a 1-byte call to a fixed vector address $= n \times 8$ (e.g. RST 1 → 0008H, RST 7 → 0038H). It also pushes PC and jumps, returning via RET, but only to one of the eight predefined locations. It is faster/shorter and is used mainly for interrupt service routines.

Summary: CALL gives flexible addressing (any address, conditional, 3 bytes); RST n is a compact, fixed-address (8 fixed vectors, 1 byte) restart used chiefly by hardware/software interrupts.

Segment Registers of the 8086

The 8086 divides its 1 MB memory into 64 KB segments, each pointed to by a 16-bit segment register:

• CS (Code Segment): Points to the segment holding program code; combined with IP to fetch instructions.
• DS (Data Segment): Points to the segment holding program data; default for data operand references (with offset from BX, SI, DI or direct).
• SS (Stack Segment): Points to the stack segment; combined with SP/BP for stack operations (PUSH, POP, CALL/RET).
• ES (Extra Segment): An additional data segment, default destination for string instructions (used with DI).

Physical address $= \text{Segment} \times 16 + \text{Offset}$.

Based, Indexed, and Based-Indexed Addressing

The effective address (offset) is formed from base registers (BX, BP), index registers (SI, DI) and a displacement.

• Based addressing: Offset = base register (BX or BP) + optional displacement.
  • Example: MOV AX, [BX] or MOV AX, [BX+4]. EA = BX (+ disp); useful for accessing structure/record fields.
• Indexed addressing: Offset = index register (SI or DI) + optional displacement.
  • Example: MOV AX, [SI] or MOV AX, [DI+2]. EA = SI (+ disp); useful for stepping through arrays.
• Based-indexed addressing: Offset = base register + index register (+ optional displacement).
  • Example: MOV AX, [BX+SI] or MOV AX, [BX+DI+6]. EA = BX + SI (+ disp); useful for two-dimensional arrays / array-of-records access.

Opcode Fetch Machine Cycle of the 8085

The opcode fetch is the first machine cycle of every instruction and takes four T-states (T1–T4) — three for the bus transfer and one extra for the CPU to decode the opcode.

Timing diagram (described state by state):

• T1: The higher address A8–A15 and the lower address A0–A7 (on AD0–AD7) are placed on the bus. ALE = 1 (high pulse) so the external latch captures A0–A7. IO/M = 0 (memory operation), with status $S_1=1, S_0=1$ indicating opcode fetch. ALE falls at the end of T1.
• T2: $\overline{RD}$ goes low (active), enabling memory to drive the opcode onto AD0–AD7. The CPU starts reading. (READY is sampled; a WAIT state is inserted if memory is slow.)
• T3: The opcode is read from AD0–AD7 into the instruction register; $\overline{RD}$ goes high (inactive) at the end of T3.
• T4: No bus activity. The CPU decodes the fetched opcode internally to determine the next operations.

Signal summary: ALE pulses high only in T1; $\overline{RD}$ is low during T2–T3; IO/M stays low (= 0) throughout (memory access).

Why four T-states? The simplest memory read (e.g. operand read) needs only three T-states (address, read, latch data). The opcode fetch needs one extra T-state (T4) because, after reading the opcode, the processor must decode it before it can begin the next machine cycle — hence 4 T-states.

T-state, Machine Cycle, and Instruction Cycle

• T-state: The smallest unit of timing — one subdivision of the operation, equal to one clock period. All 8085 operations are measured in T-states.
• Machine cycle: The time taken to perform one basic operation such as opcode fetch, memory read, memory write, I/O read or I/O write. Each machine cycle consists of 3 to 6 T-states.
• Instruction cycle: The total time to fetch and execute one complete instruction. It consists of one or more machine cycles (the first is always an opcode fetch).

Hierarchy: Instruction cycle ⊃ Machine cycle(s) ⊃ T-state(s).

Clock Frequency and T-state Duration

The duration of one T-state equals the operating clock period, which is the inverse of the operating clock frequency:

$$T = \frac{1}{f_{op}}$$

The 8085 internally divides the crystal/input frequency by 2, so $f_{op} = f_{crystal}/2$.

Example: With a 6 MHz crystal, $f_{op} = 3$ MHz, so one T-state $= 1/(3\times10^6) = 0.333\ \mu s$. Thus a higher clock frequency gives a shorter T-state and faster instruction execution.