BE Computer Engineering (IOE, TU) Basic Electronics Engineering (IOE, EX 451) Question Paper 2079 Nepal

(a) Formation of a p-n junction and the diode equation (6)

Formation of the junction: A p-n junction is formed when a single crystal of semiconductor is doped so that one region is p-type (excess holes) and the adjacent region is n-type (excess electrons). At the metallurgical junction, the large concentration gradient causes diffusion of holes from p to n and electrons from n to p. The departing carriers leave behind immobile ionized impurity atoms — negative acceptor ions on the p-side and positive donor ions on the n-side. This region, swept free of mobile carriers, is the depletion region, and the exposed ion charges set up a built-in electric field (and a barrier potential $V_0 \approx 0.7$ V for Si, $0.3$ V for Ge). At equilibrium the diffusion current is exactly balanced by the drift current due to this field, so the net current is zero.

Diode equation (Shockley equation): When an external voltage $V$ is applied, the barrier is lowered (forward bias) or raised (reverse bias). The current is

$$I = I_S\left(e^{\,V/\eta V_T} - 1\right)$$

where

• $I$ = diode (terminal) current,
• $I_S$ = reverse saturation current (due to minority carriers),
• $V$ = applied voltage across the junction (positive for forward bias),
• $\eta$ = ideality/emission factor ($\approx 1$ for Ge, $\approx 2$ for Si at low current),
• $V_T = kT/q$ = thermal voltage $\approx 26$ mV at room temperature ($T = 300$ K), with $k$ = Boltzmann constant, $q$ = electronic charge, $T$ = absolute temperature.

Interpretation: In forward bias $V>0$, the exponential dominates, so $I \approx I_S e^{V/\eta V_T}$ rises sharply. In reverse bias $V<0$, $e^{V/\eta V_T}\to 0$, so $I \approx -I_S$, a small constant reverse current. This explains the rectifying (one-way) nature of the diode.

(b) Positive (series) clipper, $v_i = 10\sin\omega t$ V (6)

A positive clipper removes (clips off) the positive part of the input above the diode cut-in level.

Operation (series diode pointing toward the source):

• Positive half-cycle: the diode is reverse biased and acts as an open switch, so no current flows and $v_o = 0$ (the positive peaks are clipped).
• Negative half-cycle: the diode is forward biased once $|v_i| > 0.7$ V; it conducts and the negative portion appears at the output, reduced by the cut-in drop, so $v_o = v_i + 0.7$ V (output reaches about $-9.3$ V).

Output waveform (described): A sine wave whose entire positive half is flat at 0 V, and whose negative half is the negative lobe of the sine but shifted up by 0.7 V, so its peak is about $-9.3$ V instead of $-10$ V. Thus only the lower (negative) excursion appears, clipped by one diode drop.

$$v_o = \begin{cases} 0 & v_i > -0.7\text{ V} \\ v_i + 0.7\text{ V} & v_i \le -0.7\text{ V}\end{cases}$$

(If the diode polarity is reversed, the negative half is clipped instead; the principle is identical.)

(a) Voltage-divider bias and $I_C$ derivation (7)

Circuit: An npn transistor with the base connected to the junction of two resistors $R_1$ (from $+V_{CC}$ to base) and $R_2$ (base to ground), forming a potential divider. The collector connects to $+V_{CC}$ through $R_C$, and the emitter to ground through $R_E$.

Derivation (using Thevenin's theorem at the base):

Thevenin voltage and resistance seen by the base:

$$V_{TH} = V_{CC}\frac{R_2}{R_1+R_2}, \qquad R_{TH} = R_1\,\|\,R_2 = \frac{R_1 R_2}{R_1+R_2}$$

Applying KVL around the base–emitter loop (with $I_E = (\beta+1)I_B \approx I_C$):

$$V_{TH} = I_B R_{TH} + V_{BE} + I_E R_E$$

Substituting $I_B = I_C/\beta$ and $I_E \approx I_C$:

$$\boxed{\,I_C = \dfrac{V_{TH} - V_{BE}}{\dfrac{R_{TH}}{\beta} + R_E}\,}$$

Why it is more stable than fixed bias: If $R_{TH}/\beta \ll R_E$ (the usual design condition), then $I_C \approx (V_{TH}-V_{BE})/R_E$, which is independent of $\beta$. Since $\beta$ varies widely between devices and with temperature, eliminating its influence keeps the Q-point fixed. In addition, $R_E$ provides negative (current-series) feedback: any rise in $I_C$ (e.g., due to temperature) increases the emitter voltage, reducing $V_{BE}$ and hence $I_C$, automatically stabilising the operating point. Fixed bias has neither feature, so its Q-point drifts strongly with $\beta$ and temperature.

(b) Q-point calculation (5)

Given $V_{CC}=18$ V, $R_1=39$ k$\Omega$, $R_2=10$ k$\Omega$, $R_C=2$ k$\Omega$, $R_E=1$ k$\Omega$, $\beta=120$, $V_{BE}=0.7$ V.

$$V_{TH} = 18\times\frac{10}{39+10} = 18\times\frac{10}{49} = 3.673\text{ V}$$ $$R_{TH} = \frac{39\times10}{49} = 7.959\text{ k}\Omega$$ $$I_{CQ} = \frac{V_{TH}-V_{BE}}{\dfrac{R_{TH}}{\beta}+R_E} = \frac{3.673-0.7}{\dfrac{7.959}{120}+1}\text{ k}\Omega = \frac{2.973}{0.0663+1} = \frac{2.973}{1.0663}\text{ mA}$$ $$\boxed{I_{CQ} \approx 2.79\text{ mA}}$$ $$V_{CEQ} = V_{CC} - I_{CQ}(R_C + R_E) = 18 - 2.79\times(2+1) = 18 - 8.37$$ $$\boxed{V_{CEQ} \approx 9.63\text{ V}}$$

The Q-point lies near the middle of the load line, confirming a well-designed bias.

(a) Ideal op-amp and inverting-amplifier gain (8)

Definition: An ideal operational amplifier is a direct-coupled, high-gain differential amplifier that amplifies the difference between its two input voltages, $v_o = A_{OL}(v_+ - v_-)$, with $A_{OL}\to\infty$.

Four ideal characteristics:

1. Infinite open-loop voltage gain, $A_{OL} = \infty$.
2. Infinite input impedance, $Z_{in} = \infty$ (no input current).
3. Zero output impedance, $Z_{out} = 0$.
4. Infinite bandwidth and infinite CMRR (zero offset, zero common-mode response).

Inverting amplifier gain (virtual-ground concept):

The input $v_i$ feeds the inverting terminal through $R_1$; $R_f$ provides feedback from output to the inverting input; the non-inverting input is grounded. Because $A_{OL}$ is infinite, the differential input voltage is essentially zero, so $v_- = v_+ = 0$ — the inverting node is a virtual ground. Also, no current enters the op-amp input, so all the current through $R_1$ flows through $R_f$:

$$\frac{v_i - 0}{R_1} = \frac{0 - v_o}{R_f}$$ $$\boxed{A_v = \frac{v_o}{v_i} = -\frac{R_f}{R_1}}$$

The negative sign indicates a $180^\circ$ phase inversion; the gain magnitude is set only by the resistor ratio.

(b) Summing amplifier for $v_o = -(2v_1 + 4v_2 + v_3)$ (5)

For an inverting summer with $R_f$ common feedback resistor:

$$v_o = -\left(\frac{R_f}{R_1}v_1 + \frac{R_f}{R_2}v_2 + \frac{R_f}{R_3}v_3\right)$$

Match coefficients with $R_f = 40$ k$\Omega$:

• $\dfrac{R_f}{R_1} = 2 \Rightarrow R_1 = \dfrac{40}{2} = 20\text{ k}\Omega$
• $\dfrac{R_f}{R_2} = 4 \Rightarrow R_2 = \dfrac{40}{4} = 10\text{ k}\Omega$
• $\dfrac{R_f}{R_3} = 1 \Rightarrow R_3 = \dfrac{40}{1} = 40\text{ k}\Omega$

Result: $R_1 = 20$ k$\Omega$, $R_2 = 10$ k$\Omega$, $R_3 = 40$ k$\Omega$, $R_f = 40$ k$\Omega$, with all three inputs applied to the inverting node and the non-inverting input grounded.

(c) Op-amp integrator (3)

Circuit: Same as an inverting amplifier but the feedback resistor $R_f$ is replaced by a capacitor $C$; the input resistor is $R$. The non-inverting input is grounded, so the inverting node is a virtual ground.

Working: Input current $i = v_i/R$ flows into the capacitor (no current into the op-amp), charging it. Since $v_- = 0$, the output equals the voltage across $C$:

$$i = \frac{v_i}{R} = -C\frac{dv_o}{dt}$$

Integrating:

$$\boxed{v_o = -\frac{1}{RC}\int_0^t v_i\,dt + v_o(0)}$$

Thus the output is the (scaled, inverted) time integral of the input — a square-wave input produces a triangular output. A large resistor is usually placed across $C$ to limit DC gain and prevent saturation from offset.

(a) n-channel JFET: construction, operation and characteristics (8)

Construction: An n-channel JFET consists of a bar of n-type semiconductor (the channel) with ohmic contacts at the two ends called the drain (D) and source (S). Two heavily doped p-type regions are diffused on the sides and connected together as the gate (G), forming two p-n junctions with the channel. The depletion regions of these reverse-biased junctions control the channel width.

Operation: The gate–source junction is always reverse biased ($V_{GS}\le 0$).

• With $V_{GS}=0$ and a small $V_{DS}$, the channel behaves like a resistor and $I_D$ rises almost linearly (ohmic region).
• As $V_{DS}$ increases, the reverse bias (and hence depletion width) is larger near the drain end, narrowing the channel. At $V_{DS}=V_P$ (the pinch-off voltage) the channel just pinches off near the drain and $I_D$ saturates at $I_{DSS}$ (drain-to-source saturation current).
• Making $V_{GS}$ more negative widens the depletion region, narrows the channel and reduces $I_D$. At $V_{GS}=V_{GS(off)}=-V_P$ the channel is fully cut off and $I_D=0$.

Transfer characteristic follows Shockley's equation:

$$I_D = I_{DSS}\left(1-\frac{V_{GS}}{V_{GS(off)}}\right)^2$$

Drain characteristics (described): A family of curves of $I_D$ vs $V_{DS}$ for different $V_{GS}$. Each curve rises steeply in the ohmic region up to the pinch-off, then flattens into the saturation (active) region where $I_D$ is nearly constant; the topmost curve is for $V_{GS}=0$ (giving $I_{DSS}$). Beyond a high $V_{DS}$, breakdown occurs. The locus where each curve enters saturation marks $V_{DS}=V_P+V_{GS}$.

Transfer characteristic (described): A single parabolic curve of $I_D$ vs $V_{GS}$, starting at $I_D=I_{DSS}$ when $V_{GS}=0$ and falling to $I_D=0$ at $V_{GS}=V_{GS(off)}$ (the pinch-off/cut-off voltage on the gate axis).

(b) Depletion-type vs enhancement-type MOSFET (4)

Full-wave bridge rectifier

Circuit (described): Four diodes $D_1$–$D_4$ arranged in a bridge. The AC secondary of the transformer connects across one diagonal of the bridge; the load $R_L$ connects across the other diagonal. No centre-tapped transformer is required.

Operation:

• Positive half-cycle: diodes $D_1$ and $D_2$ are forward biased and conduct; $D_3, D_4$ are off. Current flows through $R_L$ in a fixed direction.
• Negative half-cycle: diodes $D_3$ and $D_4$ conduct; $D_1, D_2$ are off. Current again flows through $R_L$ in the same direction.

Thus both half-cycles produce a unidirectional output.

Waveforms (described): The input is a full sine wave (alternating + and −). The output is a series of positive humps — both halves of the sine appear as positive pulses at twice the input frequency (the negative half is flipped up).

Ripple factor derivation: The ripple factor is defined as

$$\gamma = \frac{\text{rms value of AC (ripple) component}}{\text{DC value}} = \frac{V_{r(rms)}}{V_{dc}} = \sqrt{\left(\frac{V_{rms}}{V_{dc}}\right)^2 - 1}$$

For a full-wave output: $V_{dc} = \dfrac{2V_m}{\pi}$ and $V_{rms} = \dfrac{V_m}{\sqrt2}$.

$$\frac{V_{rms}}{V_{dc}} = \frac{V_m/\sqrt2}{2V_m/\pi} = \frac{\pi}{2\sqrt2} = 1.11$$ $$\gamma = \sqrt{1.11^2 - 1} = \sqrt{0.234} \approx \boxed{0.482}$$

So a full-wave rectifier has a ripple factor of about 0.48 (versus 1.21 for half-wave) — much smoother.

Capacitor filter: A large capacitor $C$ is connected in parallel with $R_L$. It charges to near the peak $V_m$ during each conducting interval and then discharges slowly through $R_L$ between peaks. This stores charge and supplies the load when the rectified voltage falls, so the output stays close to $V_m$ with only a small sawtooth ripple. The ripple factor with a capacitor filter is

$$\gamma = \frac{1}{4\sqrt3\,f R_L C}$$

showing that a larger $C$ (and $R_L$) and higher frequency reduce the ripple.

(a) Convert $(2AF.C)_{16}$ to decimal and binary (3)

To decimal — multiply each digit by its positional weight (A=10, F=15, C=12):

$$2\times16^2 + 10\times16^1 + 15\times16^0 + 12\times16^{-1}$$ $$= 512 + 160 + 15 + 0.75 = \boxed{(687.75)_{10}}$$

To binary — convert each hex digit to 4 bits:

$$2=0010,\; A=1010,\; F=1111,\; C=1100$$ $$(2AF.C)_{16} = \boxed{(0010\,1010\,1111.1100)_2}$$

Dropping leading/trailing zeros: $(1010101111.11)_2$. (Check: $1010101111_2 = 687$, $.11_2 = 0.75$.)

(b) $(1011)_2 - (0110)_2$ using 2's complement (3)

Minuend $1011_2 = 11$, subtrahend $0110_2 = 6$; expect $11-6 = 5 = 0101_2$.

Step 1 — 2's complement of $0110$: invert → $1001$; add 1 → $1010$.

Step 2 — add to minuend:

  1011
+ 1010
------
1 0101   <- carry-out = 1

Step 3 — interpretation: A carry-out of 1 means the result is positive; discard the carry. Result $= 0101_2$.

Verification: $(0101)_2 = 5 = 11 - 6$. ✓

(a) De Morgan's theorems (3)

Theorem 1: The complement of a sum equals the product of the complements.

$$\overline{A+B} = \bar{A}\cdot\bar{B}$$

Theorem 2: The complement of a product equals the sum of the complements.

$$\overline{A\cdot B} = \bar{A}+\bar{B}$$

Proof by truth table (Theorem 1):

Columns $\overline{A+B}$ and $\bar A\bar B$ are identical, proving Theorem 1. Theorem 2 is proved identically (the $\overline{A\cdot B}$ and $\bar A + \bar B$ columns match: 1,1,1,0).

(b) K-map simplification of $F=\sum m(0,1,2,5,8,9,10)$ (5)

Plot the minterms on a 4-variable K-map (rows $AB$, columns $CD$, Gray-code order 00,01,11,10):

Grouping:

• Quad m0,m2,m8,m10 (the four corners): $C=0$ and $D=0$ → term $\bar C\bar D$.
• Quad m0,m1,m8,m9 ($B=0,C=0$): → term $\bar B\bar C$.
• Pair m1,m5 ($A=0,C=0,D=1$): → term $\bar A\bar C D$.

Simplified SOP:

$$\boxed{F = \bar C\bar D + \bar B\bar C + \bar A\bar C D}$$

NAND-only implementation: Convert SOP to NAND-NAND. Each product term is formed by a NAND gate (giving its complement), and the outputs are combined by a final NAND gate, since

$$F = \overline{\overline{(\bar C\bar D)}\cdot\overline{(\bar B\bar C)}\cdot\overline{(\bar A\bar C D)}}$$

So: three first-level NAND gates produce $\overline{\bar C\bar D}$, $\overline{\bar B\bar C}$, $\overline{\bar A\bar C D}$ (inputs are the complemented literals obtained from NAND-as-inverters), and a fourth NAND gate combines them to give $F$. This is the standard two-level NAND-NAND network.

Barkhausen criterion

For sustained (self-starting, constant-amplitude) sinusoidal oscillations in a feedback amplifier with amplifier gain $A$ and feedback factor $\beta$, the loop gain must satisfy:

1. Magnitude condition: $|A\beta| = 1$ (the loop gain magnitude equals unity).
2. Phase condition: the total phase shift around the loop is $0^\circ$ (or $360^\circ$), i.e. $\angle A\beta = 0$, so feedback is positive.

(For oscillations to build up initially, $|A\beta|$ is made slightly greater than 1, then settles to 1 by amplitude limiting.)

RC phase-shift oscillator

Block diagram (described): An inverting amplifier (gain $-A$, providing $180^\circ$ phase shift) whose output is fed back to its input through a three-section RC ladder network. Each RC section contributes a phase shift, and the three sections together provide an additional $180^\circ$ at one particular frequency. Total loop phase $= 180^\circ + 180^\circ = 360^\circ$, satisfying Barkhausen's phase condition.

Working: The amplifier inverts ($180^\circ$). The RC network is designed so that at the oscillation frequency it adds exactly $180^\circ$ more. At that frequency the loop phase is $360^\circ$ and the amplifier supplies enough gain to make $|A\beta|=1$, so oscillations are sustained. The RC network attenuates the signal by a factor of $1/29$, so the amplifier must provide a gain of at least 29 to start and maintain oscillation.

Frequency of oscillation (three equal RC sections):

$$\boxed{f = \frac{1}{2\pi RC\sqrt6}}$$

It is used to generate low/audio-frequency sine waves.

Zener diode as a voltage regulator

A Zener diode is operated in reverse breakdown, where it maintains a nearly constant voltage $V_Z$ across itself over a wide range of reverse current. In a regulator it is connected in parallel with the load $R_L$, with a series resistor $R_S$ between the unregulated input and the Zener/load node.

• The series resistor $R_S$ drops the excess voltage: $I_S R_S = V_{in} - V_Z$.
• The Zener acts as a shunt: if the load draws less current, the extra current flows through the Zener; if the load draws more, the Zener current decreases. In both cases the node voltage (and hence load voltage) stays clamped at $V_Z$, giving regulation against changes in load and input.

Numerical solution

Given $V_Z=10$ V, $R_S=1$ k$\Omega$, $V_{in}=20$ V, $R_L=2$ k$\Omega$.

Series current (through $R_S$):

$$I_S = \frac{V_{in}-V_Z}{R_S} = \frac{20-10}{1\text{ k}\Omega} = 10\text{ mA}$$

Load current (load sees $V_Z=10$ V):

$$I_L = \frac{V_Z}{R_L} = \frac{10}{2\text{ k}\Omega} = 5\text{ mA}$$

Zener current (KCL: $I_S = I_Z + I_L$):

$$I_Z = I_S - I_L = 10 - 5 = \boxed{5\text{ mA}}$$

BJT common-emitter characteristics

In the CE configuration the emitter is common to input (base) and output (collector); input is $V_{BE}$/$I_B$, output is $V_{CE}$/$I_C$.

Input characteristics ($I_B$ vs $V_{BE}$ at constant $V_{CE}$, described): The curve resembles a forward-biased diode characteristic: $I_B$ is almost zero until $V_{BE}$ reaches the cut-in voltage (~0.7 V for Si), then rises sharply. Increasing $V_{CE}$ shifts the curve slightly to the right (Early effect), so for a given $V_{BE}$, $I_B$ decreases slightly. The input resistance $h_{ie} = \Delta V_{BE}/\Delta I_B$ is obtained from its slope.

Output characteristics ($I_C$ vs $V_{CE}$ for various constant $I_B$, described): A family of curves, one for each $I_B$. Each curve rises steeply for small $V_{CE}$, then becomes nearly flat (horizontal), with higher $I_B$ giving higher $I_C$. Three regions are identified:

• Saturation region: the steep, low-$V_{CE}$ portion (typically $V_{CE} < 0.2$ V). Both junctions forward biased; $I_C$ no longer controlled by $I_B$; transistor acts as a closed switch.
• Active region: the flat portion where $V_{CE}$ exceeds ~0.2 V. Emitter junction forward biased, collector junction reverse biased; $I_C \approx \beta I_B$, nearly independent of $V_{CE}$ — used for linear amplification.
• Cut-off region: the bottom curve where $I_B = 0$ (and $V_{BE}$ below cut-in). Both junctions reverse biased; only a tiny leakage current $I_{CEO}$ flows; transistor acts as an open switch.

The slight upward slope of the active-region curves is due to the Early effect (base-width modulation).

(a) Op-amp parameter definitions (4)

CMRR (Common-Mode Rejection Ratio): The ratio of the differential-mode gain $A_d$ to the common-mode gain $A_{cm}$, expressing how well the op-amp rejects signals common to both inputs:

$$\text{CMRR} = \left|\frac{A_d}{A_{cm}}\right|, \qquad \text{CMRR(dB)} = 20\log_{10}\left|\frac{A_d}{A_{cm}}\right|$$

A high CMRR (ideally infinite) is desirable.

Slew rate (SR): The maximum rate of change of the output voltage per unit time, in V/µs:

$$\text{SR} = \left.\frac{dv_o}{dt}\right|_{max}$$

It limits the largest undistorted output frequency/amplitude (a finite SR causes large-signal distortion).

Input offset voltage ($V_{io}$): The small differential DC voltage that must be applied between the two input terminals to force the output to exactly zero. It arises from mismatch in the input stage and is ideally zero.

(b) Op-amp Schmitt trigger (4)

Circuit (described): A comparator with positive feedback. The input signal is applied to the inverting input; a fraction of the output is fed back to the non-inverting input through a divider $R_1$ (from output) and $R_2$ (to ground/reference). This makes the threshold voltage depend on the output state.

Operation — hysteresis: With output at $+V_{sat}$, the non-inverting input is held at the upper threshold $V_{UT}=+V_{sat}\,\dfrac{R_2}{R_1+R_2}$. The output stays high until $v_{in}$ rises above $V_{UT}$; then it snaps to $-V_{sat}$, and the threshold drops to the lower threshold $V_{LT}=-V_{sat}\,\dfrac{R_2}{R_1+R_2}$. The output stays low until $v_{in}$ falls below $V_{LT}$, when it snaps back high. The difference $V_H = V_{UT}-V_{LT}$ is the hysteresis.

Transfer characteristic (described): A rectangular hysteresis loop: as $v_{in}$ increases the output switches high→low at $V_{UT}$; as $v_{in}$ decreases it switches low→high at $V_{LT}$, giving two distinct switching points.

Application: Squaring up a noisy or slowly-varying signal into a clean rectangular waveform (e.g., a zero-crossing/wave-shaping circuit), where the hysteresis prevents false multiple triggering due to noise.