BE Computer Engineering (IOE, TU) Basic Electronics Engineering (IOE, EX 451) Question Paper 2078 Nepal

(a) CE Characteristics of an n-p-n Transistor

In the common-emitter (CE) configuration the emitter is common to both input and output, the base is the input terminal and the collector is the output terminal.

Input characteristics — plot of base current $I_B$ versus base–emitter voltage $V_{BE}$ for fixed $V_{CE}$.

• The curve resembles a forward-biased diode: $I_B$ is negligible until $V_{BE}\approx 0.7\,\text{V}$, after which it rises sharply.
• For a higher $V_{CE}$ the curve shifts slightly to the right (Early effect widens the depletion region, reducing $I_B$).

Output characteristics — plot of collector current $I_C$ versus $V_{CE}$ for several fixed values of $I_B$. Three regions appear:

In the active region the curves are almost horizontal and equally spaced (spacing $=\beta\,\Delta I_B$); the small upward slope is due to the Early effect.

(b) Operating Point of the Voltage-Divider Bias

Thevenin equivalent of the base divider:

$$V_{TH} = V_{CC}\frac{R_2}{R_1+R_2} = 12\times\frac{10}{50} = 2.4\,\text{V}, \qquad R_{TH} = R_1\Vert R_2 = \frac{40\times10}{50} = 8\,\text{k}\Omega$$

Base loop (KVL):

$$I_B = \frac{V_{TH}-V_{BE}}{R_{TH}+(\beta+1)R_E} = \frac{2.4-0.7}{8\text{k}+101\times1\text{k}} = \frac{1.7}{109\,\text{k}} = 15.6\,\mu\text{A}$$ $$\boxed{I_{CQ} = \beta I_B = 100\times15.6\,\mu\text{A} \approx 1.56\,\text{mA}}$$

Collector loop:

$$V_{CEQ} = V_{CC} - I_C(R_C+R_E) = 12 - 1.56\text{m}\times(2\text{k}+1\text{k}) = 12 - 4.68 \approx 7.32\,\text{V}$$

Stability: Since $R_{TH}=8\,\text{k}\Omega \ll (\beta+1)R_E = 101\,\text{k}\Omega$, the base voltage is essentially fixed by the divider and the emitter resistor provides strong negative feedback. The Q-point is therefore stable and almost independent of $\beta$, making voltage-divider bias the most stable of the common biasing schemes.

(a) Ideal Op-Amp Characteristics and Virtual Ground

An ideal operational amplifier has:

1. Infinite open-loop gain ($A_{OL}\to\infty$).
2. Infinite input impedance ($Z_{in}\to\infty$) — no current enters the input terminals ($I_+ = I_- = 0$).
3. Zero output impedance ($Z_{out}=0$).
4. Infinite bandwidth and infinite slew rate.
5. Zero input offset voltage ($V_o=0$ when $V_+=V_-$).
6. Infinite CMRR (rejects common-mode signals completely).

Virtual ground: With negative feedback and infinite gain, the differential input voltage must be (almost) zero, so $V_- \approx V_+$ (the virtual short rule). In the inverting configuration the non-inverting input is grounded, hence $V_- \approx 0$. The inverting node is held at $0\,\text{V}$ without being physically connected to ground — this is the virtual ground. It lets us write $I_{in}=V_{in}/R_1$ and force all of it through the feedback resistor, giving the simple closed-loop gain $-R_f/R_1$.

(b) Summing Amplifier Design for $V_o = -(3V_1+5V_2+2V_3)$

Use an inverting summing amplifier. For an inverting adder:

$$V_o = -\left(\frac{R_f}{R_1}V_1 + \frac{R_f}{R_2}V_2 + \frac{R_f}{R_3}V_3\right)$$

Required gains: $R_f/R_1=3,\; R_f/R_2=5,\; R_f/R_3=2$.

Choose $R_f = 30\,\text{k}\Omega$ (a convenient common multiple). Then:

$$R_1 = \frac{30\text{k}}{3}=10\,\text{k}\Omega,\quad R_2 = \frac{30\text{k}}{5}=6\,\text{k}\Omega,\quad R_3 = \frac{30\text{k}}{2}=15\,\text{k}\Omega$$

Circuit (described):

• $V_1,V_2,V_3$ feed through $R_1,R_2,R_3$ to the inverting input (the summing/virtual-ground node).
• $R_f=30\,\text{k}\Omega$ connects from output back to the inverting input.
• The non-inverting input is grounded (for bias-current balance, place $R_b = R_1\Vert R_2\Vert R_3\Vert R_f \approx 2.7\,\text{k}\Omega$ to ground).

Assumptions: ideal op-amp, symmetric dual supply, signals within the linear output range.

(a) Full-Wave Bridge Rectifier

Circuit: Four diodes $D_1\!-\!D_4$ arranged in a bridge; the transformer secondary connects across one diagonal and the load $R_L$ across the other. No centre-tapped transformer is needed.

Operation:

• Positive half-cycle: $D_1$ and $D_3$ conduct, $D_2,D_4$ are OFF; current flows through $R_L$ in one direction.
• Negative half-cycle: $D_2$ and $D_4$ conduct, $D_1,D_3$ are OFF; current flows through $R_L$ in the same direction.

Thus both half-cycles produce a unidirectional output. The output waveform is a series of positive half-sine humps at twice the input frequency ($2f$).

Average (DC) output voltage:

$$V_{dc} = \frac{1}{\pi}\int_0^{\pi} V_m\sin\theta\,d\theta = \frac{2V_m}{\pi} \approx 0.637\,V_m, \qquad I_{dc}=\frac{2I_m}{\pi}$$

RMS output: $V_{rms}=V_m/\sqrt{2}$.

Ripple factor:

$$r = \frac{V_{ac(rms)}}{V_{dc}} = \sqrt{\left(\frac{V_{rms}}{V_{dc}}\right)^2 - 1} = \sqrt{\left(\frac{V_m/\sqrt2}{2V_m/\pi}\right)^2 - 1} = \sqrt{\frac{\pi^2}{8}-1} \approx \mathbf{0.482}$$

(Compared with $1.21$ for a half-wave rectifier, the bridge has much lower ripple and higher efficiency, $\eta\approx81.2\%$.)

(b) Numerical — Capacitor-Filtered Bridge

Given $V_m=30\,\text{V}$, $C=470\,\mu\text{F}$, $R_L=1\,\text{k}\Omega$, mains $f=50\,\text{Hz}$ (ripple frequency $2f=100\,\text{Hz}$).

For a capacitor filter, peak-to-peak ripple:

$$V_{r(pp)} = \frac{I_{dc}}{2fC} = \frac{V_{dc}}{2fC\,R_L}$$

First approximate $V_{dc}\approx V_m = 30\,\text{V}$, so $I_{dc}=30/1000 = 30\,\text{mA}$:

$$V_{r(pp)} = \frac{30\times10^{-3}}{2\times50\times470\times10^{-6}} = \frac{0.03}{0.047} \approx \mathbf{0.64\,\text{V}}$$

More exact DC output:

$$V_{dc} \approx V_m - \frac{V_{r(pp)}}{2} = 30 - 0.32 \approx \mathbf{29.7\,\text{V}}$$

Result: $V_{dc}\approx 29.7\,\text{V}$ with a peak-to-peak ripple of about $0.64\,\text{V}$.

(a) n-Channel Enhancement MOSFET

Construction: Built on a lightly doped p-type substrate. Two heavily doped n+ regions (source and drain) are diffused into it but are not connected by a continuous n-channel at fabrication. A thin SiO₂ insulating layer is grown over the region between source and drain, and a metal/poly gate is deposited on top, forming a metal–oxide–semiconductor capacitor.

Operation:

• With $V_{GS}=0$ there is no channel (two back-to-back p-n junctions block current) → $I_D=0$.
• As a positive $V_{GS}$ is applied, it repels holes and attracts electrons to the surface under the oxide. When $V_{GS}$ exceeds the threshold voltage $V_T$, an inversion layer (n-channel) forms, connecting source and drain — the device turns ON. Increasing $V_{GS}$ enhances the channel and increases $I_D$, hence "enhancement type".
• For $V_{DS}>V_{GS}-V_T$ the channel pinches off at the drain end and $I_D$ saturates.

Threshold voltage $V_T$: the minimum gate-to-source voltage required to form the conducting inversion channel (typically $+1$ to $+3\,\text{V}$ for an n-channel enhancement MOSFET).

Drain characteristics ($I_D$ vs $V_{DS}$): for each $V_{GS}>V_T$, $I_D$ rises (ohmic/triode region) then flattens (saturation region).

Transfer characteristic ($I_D$ vs $V_{GS}$): zero until $V_{GS}=V_T$, then rises parabolically following

$$I_D = k\,(V_{GS}-V_T)^2.$$

(b) JFET vs BJT Comparison

'Unipolar device': A JFET (and any FET) is called unipolar because conduction is carried out by only one type of charge carrier — majority carriers (electrons in an n-channel, holes in a p-channel) — whereas a BJT relies on both majority and minority carriers (bipolar).

Positive Clipper

Circuit: A diode in series with the load, oriented so it conducts on the negative half and blocks the positive half. (Series resistor $R$ feeds the input; diode cathode toward input so that the positive part is clipped.)

Operation: During the positive half-cycle the diode is reverse biased (open) and the output across the load is clipped to ~$0\,\text{V}$ (ideally). During the negative half-cycle the diode conducts and the output follows the input.

Output for $\pm10\,\text{V}$ sine: the positive peaks are removed; the waveform sits between $0\,\text{V}$ and $-10\,\text{V}$ (only the negative half-sine appears, about $-9.3\,\text{V}$ peak allowing for the $0.7\,\text{V}$ diode drop). The DC level is unchanged — clipping reshapes the wave.

Positive Clamper

Circuit: A series capacitor $C$ followed by a diode in shunt (to ground), with the diode oriented to conduct during the negative half-cycle. A clamper requires a capacitor and a diode.

Operation: On the first negative half-cycle the diode conducts and charges $C$ to nearly $V_m=10\,\text{V}$. Thereafter the diode is open and the charged capacitor adds a constant $+10\,\text{V}$ offset in series with the input.

Output for $\pm10\,\text{V}$ sine: the entire waveform is shifted up by $V_m$. The output swings from $0\,\text{V}$ (negative peaks clamped to ground) to about $+20\,\text{V}$ (positive peaks). The shape is preserved, only the DC level is shifted — this is the key difference from a clipper.

Summary: A clipper removes part of the waveform (changes shape); a clamper shifts the whole waveform to a new DC reference (preserves shape).

Zener Voltage Regulator Calculation

Given: $V_Z=6.2\,\text{V}$, $R_S=220\,\Omega$, $V_{in}=12\,\text{V}$, $I_L=15\,\text{mA}$.

Series (source) current through $R_S$ — the regulated node sits at $V_Z=6.2\,\text{V}$:

$$I_S = \frac{V_{in}-V_Z}{R_S} = \frac{12-6.2}{220} = \frac{5.8}{220} = 26.4\,\text{mA}$$

Zener current (KCL: $I_S = I_Z + I_L$):

$$\boxed{I_Z = I_S - I_L = 26.4 - 15 = 11.4\,\text{mA}}$$

Power dissipated in the Zener:

$$\boxed{P_Z = V_Z\,I_Z = 6.2\times11.4\,\text{mA} \approx 70.7\,\text{mW}}$$

Condition for Regulation

For the regulator to hold the output at $V_Z$, the Zener must stay in reverse breakdown, i.e. the Zener current must remain between its minimum and maximum limits:

$$I_{Z(min)} \le I_Z \le I_{Z(max)}$$

Equivalently the input voltage and load current must be such that $I_Z>I_{Z(min)}$ (so the diode stays in breakdown) and $I_Z<P_{Z(max)}/V_Z$ (so it is not destroyed). If the load draws so much current that $I_Z$ falls to zero, regulation is lost.

(a) Convert $(2A.5)_{16}$

To decimal:

$$2\times16^1 + 10\times16^0 + 5\times16^{-1} = 32 + 10 + 0.3125 = \boxed{(42.3125)_{10}}$$

To binary (replace each hex digit by 4 bits): $2=0010,\; A=1010,\; 5=0101$:

$$(2A.5)_{16} = \boxed{(0010\,1010.0101)_2} = (101010.0101)_2$$

(b) Subtraction by 2's Complement

Compute $(10110010)_2 - (01101101)_2$, i.e. $178 - 109$.

Step 1 — 2's complement of the subtrahend $01101101$:

• 1's complement: $10010010$
• add 1: $10010011$

Step 2 — add to minuend:

   1011 0010   (178)
 + 1001 0011   (2's comp of 109)
 -----------
 1 0100 0101

Step 3 — discard the end carry (carry-out = 1 → result is positive):

$$\text{Result} = (0100\,0101)_2 = \boxed{(69)_{10}}$$

Verification: $178 - 109 = 69$. ✓

(a) De Morgan's Theorems

Theorem 1: $\overline{A+B} = \bar{A}\cdot\bar{B}$ — the complement of a sum equals the product of complements.

Theorem 2: $\overline{A\cdot B} = \bar{A}+\bar{B}$ — the complement of a product equals the sum of complements.

Proof by truth table (Theorem 1):

Columns 3 and 4 are identical for all inputs, so $\overline{A+B}=\bar{A}\bar{B}$. The truth table for Theorem 2 is verified identically, confirming $\overline{AB}=\bar A+\bar B$.

(b) Simplify and Implement with NAND

$$F = A\bar{B} + AB + \bar{A}B$$

Group the first two terms: $A\bar B + AB = A(\bar B + B) = A$. Then:

$$F = A + \bar{A}B$$

Using the absorption identity $A+\bar A B = A+B$:

$$\boxed{F = A + B}$$

NAND-only implementation: an OR gate equals a NAND of the inverted inputs, and inverters are NAND gates with tied inputs. By De Morgan, $A+B = \overline{\bar A \cdot \bar B}$:

A ──►[NAND]──► A̅      (NAND1: inputs A,A)
B ──►[NAND]──► B̅      (NAND2: inputs B,B)
A̅,B̅ ─►[NAND]──► F = A+B   (NAND3)

Thus three NAND gates: two as inverters producing $\bar A,\bar B$, and one combining them, since $\overline{\bar A \cdot \bar B}=A+B$.

Barkhausen Criterion

For sustained (steady) sinusoidal oscillations in a feedback amplifier, two conditions must be met simultaneously:

1. Loop gain magnitude $|A\beta| = 1$ (the product of amplifier gain $A$ and feedback factor $\beta$ is unity).
2. Total phase shift around the loop $= 0^\circ$ (or an integer multiple of $360^\circ$), i.e. the feedback must be positive.

In practice $|A\beta|$ is made slightly greater than 1 at start-up so oscillations build from noise, then amplitude limiting brings it to 1.

RC Phase-Shift Oscillator

Circuit: A single-stage common-emitter (or op-amp inverting) amplifier that gives $180^\circ$ phase shift, followed by a three-section RC ladder network in the feedback path, each section providing $60^\circ$ so the network adds another $180^\circ$. Total $=360^\circ$, satisfying the phase condition.

Working: The amplifier inverts the signal ($180^\circ$). The cascaded RC sections progressively shift the phase a further $180^\circ$ at one particular frequency. At that frequency the feedback is in phase (positive). The amplifier supplies enough gain to overcome the attenuation of the RC network (which is $1/29$), so $|A\beta|\ge1$ and oscillations are sustained.

Frequency of oscillation (three identical RC sections):

$$\boxed{f = \frac{1}{2\pi RC\sqrt{6}}}$$

and the amplifier must provide a minimum gain of $|A|\ge 29$ to satisfy $|A\beta|=1$.

Op-Amp Integrator — Input–Output Relationship

Circuit: Inverting configuration with input resistor $R$ to the inverting node and a feedback capacitor $C$ from output to that node; non-inverting input grounded.

Because of the virtual ground, the inverting node sits at $0\,\text{V}$ and no current enters the op-amp input. The input current equals the capacitor current:

$$\frac{V_{in}}{R} = -C\frac{dV_o}{dt}$$

Integrating both sides:

$$\boxed{V_o(t) = -\frac{1}{RC}\int_0^{t} V_{in}\,dt \; + \; V_o(0)}$$

So the output is the time integral of the input, scaled by $-1/RC$ (the time constant). A constant DC input therefore produces a linearly rising/falling ramp at the output.

Why a High-Value Feedback Resistor $R_f$ is Added

In an ideal integrator the capacitor presents infinite gain to DC (impedance $1/j\omega C \to\infty$ as $\omega\to0$). Consequently the op-amp's small input offset voltage and bias currents are integrated and accumulate, driving the output steadily toward saturation.

A large resistor $R_f$ placed in parallel with $C$ limits the DC gain to a finite value $-R_f/R$, providing a DC feedback path that bleeds off the charge and stabilises the operating point. It effectively converts the integrator into a lossy (practical) integrator / first-order low-pass filter: integration still occurs for frequencies above $f=1/(2\pi R_f C)$, while DC drift is suppressed.

Depletion Region in an Unbiased p-n Junction

When p- and n-type semiconductors form a junction, the large concentration gradient causes majority carriers to diffuse across: electrons from n → p and holes from p → n. Near the junction they recombine, leaving behind immobile ionised dopant atoms — negative acceptor ions on the p-side and positive donor ions on the n-side.

This layer of fixed charges, swept free of mobile carriers, is the depletion region. The exposed ions set up an internal electric field (and a barrier potential, ~0.7 V for Si, 0.3 V for Ge) that opposes further diffusion. Equilibrium is reached when the diffusion current is exactly balanced by the drift current; net current $=0$.

Under Forward Bias (p positive, n negative)

• The applied voltage opposes the barrier potential, so the barrier is reduced.
• The depletion width decreases.
• Beyond the cut-in voltage, majority carriers cross easily and a large forward current flows (rises exponentially with voltage).

Under Reverse Bias (p negative, n positive)

• The applied voltage aids the barrier potential, increasing it.
• The depletion width increases (more ions uncovered).
• Majority-carrier flow is blocked; only a tiny reverse saturation (leakage) current $I_S$ flows, due to minority carriers, and it is almost independent of the reverse voltage until breakdown.

Definitions of $\alpha$ and $\beta$

• $\alpha$ (common-base current gain): ratio of collector current to emitter current,

$$\alpha = \frac{I_C}{I_E}\quad(\text{typically } 0.95\text{–}0.99)$$

• $\beta$ (common-emitter current gain): ratio of collector current to base current,

$$\beta = \frac{I_C}{I_B}$$

Relationship Between $\alpha$ and $\beta$

From KCL, $I_E = I_C + I_B$. Dividing by $I_C$:

$$\frac{I_E}{I_C} = 1 + \frac{I_B}{I_C} \;\Rightarrow\; \frac{1}{\alpha} = 1 + \frac{1}{\beta}$$

Solving:

$$\boxed{\beta = \frac{\alpha}{1-\alpha}}, \qquad \boxed{\alpha = \frac{\beta}{1+\beta}}$$

Numerical ($\beta = 120$)

$$\alpha = \frac{\beta}{1+\beta} = \frac{120}{121} = \mathbf{0.9917}$$

Leakage Currents — $I_{CEO}$ in terms of $I_{CBO}$

• $I_{CBO}$ = collector–base leakage current with the emitter open (common-base).
• $I_{CEO}$ = collector–emitter leakage current with the base open (common-emitter).

The two are related by:

$$\boxed{I_{CEO} = (\beta+1)\,I_{CBO} = \frac{I_{CBO}}{1-\alpha}}$$

For $\beta=120$: $I_{CEO} = 121\,I_{CBO}$ — the leakage is amplified about 121 times in the CE configuration, which is why CE is more temperature-sensitive.