BE Computer Engineering (Pokhara University) Digital Logic (PU, ELX 110) Question Paper 2079
This is the official BE Computer Engineering (Pokhara University) Digital Logic (PU, ELX 110) question paper for 2079, as set in the regular annual examination. It carries 100 full marks and a time allowance of 180 minutes, across 11 questions. On Kekkei you can attempt this Digital Logic (PU, ELX 110) past paper online with a timer, get instant AI feedback and step-by-step solutions, and track the topics where you lose marks — completely free. Whether you are revising for your BE Computer Engineering (Pokhara University) Digital Logic (PU, ELX 110) exam or solving previous years' question papers, this 2079 paper is a great way to practise under real exam conditions.
Section A: Long Answer Questions
Attempt all / any as specified.
(a) Convert the following numbers as indicated, showing all steps: (i) to its decimal and octal equivalents. (ii) to its binary and decimal equivalents. (6)
(b) Perform the subtraction using the 2's complement method and verify your answer in decimal. (3)
(c) What is a weighted code? Encode the decimal number in BCD (8421) and explain why the Gray code is preferred for shaft-position encoders. (3)
(a) State and prove De Morgan's theorems. Using Boolean algebra, simplify the expression and express the result in its simplest form. (6)
(b) A logic function is given by . Use a four-variable Karnaugh map to obtain the minimal sum-of-products expression and implement it using only NAND gates. (8)
(a) Design a synchronous sequential circuit that detects the input sequence 1011 (overlapping allowed) using a Mealy model. Draw the state diagram, construct the state table, perform state assignment, and obtain the excitation equations using JK flip-flops. (10)
(b) Differentiate between a Moore machine and a Mealy machine with the help of a suitable diagram. (4)
(a) Implement the Boolean function using an 8-to-1 multiplexer. Draw the complete connection diagram. (5)
(b) Design a 3-to-8 line decoder using logic gates and show how two such decoders can be cascaded with an enable input to build a 4-to-16 line decoder. (5)
Section B: Short Answer Questions
Attempt all / any as specified.
(a) Draw the truth table of a full adder and derive the simplified expressions for the SUM and CARRY outputs. (4)
(b) Construct a 4-bit binary parallel adder using full adders and explain the limitation caused by carry-propagation delay. (4)
(a) Explain the operation of a JK flip-flop with its characteristic table and characteristic equation. What is the race-around condition and how does a master-slave configuration eliminate it? (5)
(b) Convert a D flip-flop into a T flip-flop, showing the required logic. (2)
(a) Design a MOD-6 synchronous up counter using T flip-flops and draw its timing diagram. (5)
(b) Distinguish between a synchronous counter and a ripple (asynchronous) counter. (2)
With the help of a neat logic diagram, explain the working of a 4-bit Serial-In Parallel-Out (SIPO) shift register. State two practical applications of shift registers.
(a) Express the function in canonical sum-of-products (minterm) form. (3)
(b) What are universal gates? Realize the EX-OR function using only NOR gates. (3)
(a) Design a BCD-to-seven-segment decoder, listing the truth table for the segment 'a' and obtaining its simplified expression. (4)
(b) Differentiate between an encoder and a decoder. (2)
(a) Add the BCD numbers and and explain why a correction factor is sometimes required in BCD addition. (3)
(b) Write short notes on parity bit and its use in error detection. (2)