BE Computer Engineering (Pokhara University) Computer Architecture (PU, CMP 262) Question Paper 2079
This is the official BE Computer Engineering (Pokhara University) Computer Architecture (PU, CMP 262) question paper for 2079, as set in the regular annual examination. It carries 100 full marks and a time allowance of 180 minutes, across 12 questions. On Kekkei you can attempt this Computer Architecture (PU, CMP 262) past paper online with a timer, get instant AI feedback and step-by-step solutions, and track the topics where you lose marks — completely free. Whether you are revising for your BE Computer Engineering (Pokhara University) Computer Architecture (PU, CMP 262) exam or solving previous years' question papers, this 2079 paper is a great way to practise under real exam conditions.
Section A: Long Answer Questions
Attempt all / any as specified.
(a) Differentiate between RISC and CISC instruction set architectures with respect to instruction format, addressing modes, and hardware complexity. (7)
(b) A processor supports the following addressing modes: immediate, direct, indirect, register, register-indirect, and indexed. For an instruction LOAD R1, X where the effective address is to be computed, explain with diagrams how the operand is fetched in register-indirect and indexed addressing modes, and state one practical use of each. (7)
(a) Distinguish between hardwired control and microprogrammed control units, listing two advantages and two disadvantages of each. (6)
(b) Design a microprogrammed control unit and explain the role of the control memory, control address register (CAR), control data register, and sequencing logic. Show how the next microinstruction address is selected during conditional branching. (8)
(a) Explain the principle of locality of reference and how it justifies the use of a memory hierarchy. (4)
(b) Consider a system with a cache access time of 5 ns and a main memory access time of 70 ns. If the hit ratio is 0.92, calculate the average memory access time. Then determine the new hit ratio required to reduce the average memory access time below 8 ns. (8)
(a) Explain the different types of pipeline hazards (structural, data, and control) with one example of each. (6)
(b) A non-pipelined processor takes 12 ns to execute an instruction. The same datapath is divided into a 5-stage pipeline with stage delays of 3 ns, 2 ns, 4 ns, 2 ns, and 3 ns, plus a 0.5 ns latch delay per stage. Compute the clock period, the speedup for executing 1000 instructions, and the maximum theoretical speedup. (6)
Section B: Short Answer Questions
Attempt all / any as specified.
Describe the instruction cycle of a CPU and explain the sequence of micro-operations performed during the fetch phase using register transfer language (RTL).
A direct-mapped cache has 64 blocks with a block size of 16 bytes. The main memory is 4 KB. Determine the number of bits in the TAG, LINE (block), and WORD fields of the memory address. Show how the address 0x2A7 is split across these fields.
Compare programmed I/O, interrupt-driven I/O, and Direct Memory Access (DMA) as techniques for data transfer between the CPU and I/O devices, highlighting their relative advantages in terms of CPU involvement and throughput.
State Flynn's classification of computer architectures and briefly describe each category (SISD, SIMD, MISD, MIMD) with a representative example of each.
A program spends 40% of its execution time on a section that is enhanced to run 5 times faster. Using Amdahl's law, calculate the overall speedup of the program. What is the maximum achievable speedup if the enhancement were made infinitely fast?
Explain the daisy-chaining method of bus arbitration with a suitable diagram. State one advantage and one limitation of this scheme compared to a centralized parallel arbitration scheme.
Explain the concept of virtual memory and the role of paging. Describe how a Translation Lookaside Buffer (TLB) improves the performance of address translation.
Differentiate between a multicore processor and a multiprocessor system. Briefly explain cache coherence and why it becomes a problem in shared-memory multiprocessors.