BE Computer Engineering (Pokhara University) Computer Architecture (PU, CMP 262) Question Paper 2078

(a) Differentiate between RISC and CISC instruction set architectures with respect to instruction format, addressing modes, and hardware complexity. (7)

(b) A computer has a 16-bit instruction word. The processor supports 64 distinct operations and uses a register file of 16 general-purpose registers. For a two-address register-to-register instruction, design a suitable instruction format showing the bit allocation for the opcode and operand fields. Then, using the same machine, explain with examples how the following addressing modes are interpreted: immediate, register indirect, indexed, and PC-relative. (7)

(a) Draw and explain the organization of a basic CPU showing the ALU, register set, control unit, and the system bus. Describe the role of the program counter (PC), instruction register (IR), and memory address register (MAR) during the instruction fetch cycle. (7)

(b) Compare hardwired control units with microprogrammed control units. For a microprogrammed control unit, explain the difference between horizontal and vertical microinstruction formats, and discuss the trade-off between control memory size and execution speed. (7)

(a) Explain the concept of instruction pipelining. Describe the different types of pipeline hazards (structural, data, and control) and outline one technique to resolve each. (6)

(b) A non-pipelined processor takes 5 ns to execute each instruction. The same processor is redesigned into a 5-stage pipeline where each stage takes 1 ns and the pipeline register delay between stages is 0.2 ns. Calculate the speedup achieved by the pipeline for executing 1000 instructions, assuming no stalls. Also state the theoretical maximum speedup. (6)

(a) Explain the memory hierarchy of a computer system and justify why it improves average memory access time, referring to the principle of locality of reference. (5)

(b) A system has a cache with a hit ratio of 0.95, a cache access time of 5 ns, and a main memory access time of 80 ns. Compute the average memory access time for both a simultaneous (look-aside) access scheme and a hierarchical (look-through) access scheme. (4)

(c) Compare direct-mapped, fully associative, and set-associative cache mapping techniques in terms of hardware cost, hit ratio, and search complexity. (3)

Compare programmed I/O, interrupt-driven I/O, and direct memory access (DMA) as techniques for data transfer between the CPU and I/O devices. Under what circumstances is DMA most beneficial?

State Flynn's classification of computer architectures. Briefly describe each of the four categories (SISD, SIMD, MISD, MIMD) and give one practical example of a system belonging to each category.

State Amdahl's law. A program spends 70% of its execution time in a section that can be parallelized across 8 processors, while the remaining 30% is strictly sequential. Calculate the overall speedup and explain what the result implies about the limits of parallel processing.

Explain the difference between the write-through and write-back cache write policies. Discuss the role of the dirty bit and compare the two policies in terms of memory traffic and data consistency.

Represent the decimal number -85.375 in IEEE 754 single-precision (32-bit) floating-point format. Show the sign, exponent (with bias), and mantissa fields clearly.

Write the sequence of register-transfer micro-operations required to fetch an instruction from memory and increment the program counter. Explain the purpose of each micro-operation in the fetch cycle.

Explain bus arbitration in a system with multiple bus masters. Differentiate between centralized daisy-chaining and independent request/grant schemes.

Write short notes on any TWO of the following:

(a) Cache coherence problem in multiprocessor systems

(b) Crossbar switch interconnection network

(c) Superscalar processor architecture