BE Computer Engineering (IOE, TU) Microprocessor (IOE, EX 551) Question Paper 2078

(a) With the help of a neat functional block diagram, explain the internal architecture of the 8085 microprocessor. Clearly describe the role of the ALU, the register array (including the temporary, W and Z registers), the instruction register/decoder, and the timing and control unit. [7]

(b) The 8086 uses a pipelined architecture divided into the Bus Interface Unit (BIU) and the Execution Unit (EU). Explain how this organisation achieves instruction prefetching, and state how the physical address is computed from the segment and offset registers with a suitable example. [5]

(a) Write an 8085 assembly language program to find the largest number in a block of 10 unsigned bytes stored in consecutive memory locations starting at 2050H, and store the result at 2060H. Include comments and the necessary HLT. [7]

(b) Explain, with the effect on flags, the difference between the instructions CMP B, SUB B, and CMC in the 8085 instruction set. [5]

(a) Design an interfacing circuit to connect 4 KB of EPROM (starting at address 0000H) and 2 KB of RAM (starting at address 8000H) to an 8085 microprocessor. Show the address decoding logic, the use of the ALE signal for address/data demultiplexing, and a clear memory map. [8]

(b) Differentiate between memory-mapped I/O and I/O-mapped (isolated) I/O with respect to address space, control signals used, and the instructions employed. [4]

(a) Draw the internal block diagram of the 8255A Programmable Peripheral Interface and explain the function of its three ports (A, B, C) and the group control logic. [6]

(b) The 8255A is to be operated in Mode 0 with Port A and Port C-upper as output, and Port B and Port C-lower as input. Determine the control word and explain the procedure to initialise the device. Also briefly compare Mode 1 and Mode 2 operation. [6]

Explain the different addressing modes available in the 8085 microprocessor. Give one example instruction for each mode and identify the operand location.

Describe the hardware interrupts of the 8085 (TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR) in terms of priority, vector address, and whether they are maskable or edge/level triggered. How do the SIM and RIM instructions control these interrupts?

Explain the operating modes of the 8253 programmable interval timer. Describe in particular Mode 0 (interrupt on terminal count) and Mode 3 (square wave generator), and write the format of the mode control word.

What is Direct Memory Access (DMA)? With the help of the HOLD and HLDA signals, explain how an 8085-based system carries out a DMA data transfer, and state the advantage of DMA over programmed I/O.

(a) Explain the operation of the stack and the use of the PUSH and POP instructions in the 8085, including the effect on the stack pointer. [3]

(b) What is the difference between the CALL/RET and RST n mechanisms for subroutine handling? [3]

Explain the function of the segment registers (CS, DS, SS, ES) in the 8086. With suitable examples, distinguish between based, indexed, and based-indexed addressing modes of the 8086.

Draw the timing diagram for the opcode fetch machine cycle of the 8085. Indicate the T-states, the status of the ALE, RD, and IO/M signals, and explain why the opcode fetch cycle requires four T-states.

Differentiate between machine cycle, instruction cycle, and T-state in the context of 8085 instruction execution, and explain how clock frequency relates to the duration of a T-state.