BE Computer Engineering (IOE, TU) Computer Organization and Architecture (IOE, CT 603 / ENCT 303) Question Paper 2079

(a) Draw the hardware block diagram for the Booth's multiplication algorithm and explain the function of each register. [6]

(b) Using Booth's algorithm, multiply the signed numbers (-7) × (+3) in 4-bit 2's complement representation. Show the contents of the A, Q and Q₋₁ registers after each step. [6]

A control unit can be implemented as hardwired or microprogrammed.

(a) Draw the block diagram of a microprogrammed control unit and explain the role of the control address register (CAR), control memory and sequencer. [7]

(b) Compare hardwired and microprogrammed control units on the basis of speed, flexibility, cost and implementation complexity. [5]

(a) Explain the four-segment instruction pipeline with a space-time diagram, and discuss the different types of pipeline hazards (structural, data and control) along with at least one technique to handle each. [8]

(b) A non-pipelined processor executes a task in 80 ns. Suppose the same task is divided into a 5-stage pipeline with equal stage delays and a clock skew/latch overhead of 2 ns per stage. Compute the clock period, the speedup and the throughput of the pipeline for executing 1000 instructions. [6]

Consider a main memory of size 4 K words and a cache of 128 words with a block size of 8 words.

(a) For direct mapping, determine the number of bits in the tag, line (block) and word fields of the CPU address, and draw the address format. [6]

(b) Explain set-associative mapping and, for a 2-way set-associative organization of the same cache, recompute the tag, set and word field widths. State one advantage it has over direct mapping. [6]

Write a program to evaluate the arithmetic statement X = (A + B) * (C + D) using three-address, two-address, one-address and zero-address (stack) instruction formats. Comment on the number of instructions and memory references required by each.

Explain the following addressing modes with a suitable example for each, and state one typical use: (a) immediate, (b) register indirect, (c) indexed, and (d) relative addressing. For the instruction LOAD 500, if PC = 200, R1 = 400 and memory[500] = 800, determine the effective address and the loaded operand in direct, indexed (using R1) and relative modes.

(a) Differentiate between programmed I/O, interrupt-driven I/O and DMA on the basis of CPU involvement and data transfer speed. [4]

(b) Explain how daisy chaining is used for establishing interrupt priority among multiple I/O devices. [2]

Draw the block diagram of a DMA controller and explain the cycle stealing mode of data transfer. How does the DMA controller gain control of the system bus from the CPU?

(a) State Flynn's classification of computer architectures (SISD, SIMD, MISD, MIMD) with one example of each. [4]

(b) Differentiate between tightly coupled and loosely coupled multiprocessor systems. [2]

Explain the organization of a stack in a CPU. Differentiate between a register stack and a memory stack, and show how the PUSH and POP operations modify the stack pointer (SP) in each case.

Define virtual memory. Explain paging as an address-mapping technique and describe the function of the page table and the translation lookaside buffer (TLB) in speeding up address translation.

Compare RISC and CISC architectures with respect to instruction set size, addressing modes, instruction length, use of registers and control unit implementation. Give one example processor of each type.