BE Computer Engineering (IOE, TU) Computer Organization and Architecture (IOE, CT 603 / ENCT 303) Question Paper 2078
This is the official BE Computer Engineering (IOE, TU) Computer Organization and Architecture (IOE, CT 603 / ENCT 303) question paper for 2078, as set in the regular annual examination. It carries 80 full marks and a time allowance of 180 minutes, across 12 questions. On Kekkei you can attempt this Computer Organization and Architecture (IOE, CT 603 / ENCT 303) past paper online with a timer, get instant AI feedback and step-by-step solutions, and track the topics where you lose marks — completely free. Whether you are revising for your BE Computer Engineering (IOE, TU) Computer Organization and Architecture (IOE, CT 603 / ENCT 303) exam or solving previous years' question papers, this 2078 paper is a great way to practise under real exam conditions.
Section A: Long Answer Questions
Attempt all / any as specified.
(a) Differentiate between hardwired control unit and microprogrammed control unit on the basis of speed, flexibility, implementation cost and ease of modification. [6]
(b) Design a hardwired control unit for a simple processor. Draw the block diagram showing the instruction register, sequence counter, instruction decoder and control logic gates, and explain how the control signals are generated for a fetch cycle. [6]
(a) Explain the principle of locality of reference and how the memory hierarchy exploits it to bridge the speed gap between the CPU and main memory. [4]
(b) A computer has a 256 KB main memory and a 2 KB cache with a block size of 16 bytes. Show the address format (number of tag, line/set and word bits) for (i) direct mapping and (ii) 4-way set-associative mapping. [8]
(a) What is instruction pipelining? Describe the different segments of a four-stage instruction pipeline (FI, DA, FO, EX) with the help of a space-time diagram. [6]
(b) Define pipeline hazards. Explain data hazards and control hazards, and discuss any two techniques used to handle the control hazard caused by branch instructions. [6]
(a) Draw the hardware block diagram for Booth's multiplication algorithm and explain its operation. [6]
(b) Multiply the signed numbers (-5) and (+3) using Booth's algorithm, showing the contents of the registers (A, Q, Q₋₁) at each step. [6]
Section B: Short Answer Questions
Attempt all / any as specified.
Explain the following addressing modes with a suitable example of each, and state one practical use of each: (a) immediate, (b) register indirect, (c) indexed, (d) relative addressing mode.
Differentiate between RISC and CISC architectures with respect to instruction format, addressing modes, execution and the use of registers. Give one example processor of each type.
What is an interrupt-driven I/O? With the help of a flowchart, explain how the CPU handles an interrupt request issued by an I/O device, and compare it with programmed I/O in terms of CPU utilization.
Explain the working of Direct Memory Access (DMA) with a block diagram. Describe the cycle-stealing and burst transfer modes of DMA operation.
State and explain Flynn's classification of parallel computer architectures (SISD, SIMD, MISD, MIMD) with a representative example or application of each category.
(a) List the major registers of a basic computer CPU and state the function of the Program Counter (PC), Memory Address Register (MAR) and Instruction Register (IR). [3]
(b) Write the register transfer microoperations for the fetch phase of an instruction. [3]
A processor has a cache with a hit ratio of 0.92. The cache access time is 10 ns and the main memory access time is 100 ns. (a) Compute the average memory access time. [3] (b) Explain the write-through and write-back cache write policies and state one advantage of each. [3]
Write short notes on any two of the following: (a) Vector processing and array processors, (b) Hypercube interconnection network, (c) Amdahl's law and its significance in parallel computing.