BE Computer Engineering (Pokhara University) Embedded System (PU, ELX 320) Question Paper 2079 Nepal

(a) Embedded System and General Architecture (8 marks)

Definition: An embedded system is a dedicated, application-specific computing system in which a microprocessor or microcontroller is embedded as a component to perform a specific control or processing function. It is designed to operate within a larger mechanical or electrical system, usually with real-time constraints, limited resources and little or no general-purpose user interface (e.g. washing machine controller, automotive ECU, digital camera).

Block Diagram (described)

        +---------------------------------------------------+
        |                  SYSTEM BUS                       |
        |  (Address bus | Data bus | Control bus)           |
        +----+-----------+--------------+-------------------+
             |           |              |
      +------+----+  +----+-----+  +-----+------+
      | Processing |  |  Memory  |  |   I/O       |
      |   Unit     |  | ROM/Flash|  | Subsystem   |
      | (CPU/MCU)  |  |   RAM    |  | (ports,     |
      |  ALU,CU,   |  |          |  |  ADC, timer,|
      |  Registers |  |          |  |  UART/SPI)  |
      +-----------+  +----------+  +------+------+
                                          |
                              Sensors <---+---> Actuators

Role of each block

• Processing Unit (CPU/microcontroller core): The "brain" that fetches, decodes and executes instructions. Contains the ALU (arithmetic/logic operations), the control unit (sequencing and timing) and registers. It runs the embedded firmware and makes control decisions.
• Memory: Stores program code and data.
  • ROM/Flash (non-volatile): holds the fixed application program and constant data.
  • RAM (volatile): holds variables, the stack and temporary run-time data.
• Input/Output (I/O) subsystem: Interfaces the processor with the outside world. Includes digital I/O ports, ADC/DAC, timers/counters and serial peripherals (UART, SPI, I2C) used to read sensors and drive actuators.
• System Bus: The shared set of parallel lines that connects the above blocks. It comprises the address bus (selects a memory/I/O location), the data bus (carries the data) and the control bus (read/write, clock, interrupt and timing signals).

(b) Von Neumann vs Harvard Architecture (6 marks)

Why microcontrollers (AVR, PIC) use Harvard-based design: Embedded applications need deterministic, high instruction throughput. Separate program and data buses let the MCU fetch the next instruction while accessing data for the current one, enabling near single-cycle instruction execution and pipelining. It also allows the instruction word (e.g. 14/16-bit) to be wider than the 8-bit data word, and keeps fixed program code safely in Flash separate from RAM. These benefits — speed, determinism and efficient code storage — make Harvard the natural choice for resource-constrained, real-time microcontrollers.

(a) Real-Time Operating System (6 marks)

A Real-Time Operating System (RTOS) is an operating system designed to manage tasks under strict timing constraints, guaranteeing that responses to events occur within a defined, predictable (deterministic) time bound. Correctness depends not only on the logical result but also on when the result is produced. Key features: deterministic scheduling, low and bounded interrupt latency, priority-based pre-emption and inter-task synchronization.

(b) Task Scheduling in an RTOS (8 marks)

Task scheduling is the activity by which the RTOS kernel (scheduler) decides which ready task gets the CPU at any instant. In a pre-emptive priority-based scheduler, every task has a priority; whenever a higher-priority task becomes ready, the scheduler immediately suspends (pre-empts) the running lower-priority task, saves its context, and runs the higher-priority task. Lower-priority tasks resume only when all higher-priority tasks are blocked or complete.

Scenario

Let T1 (highest priority) become ready at t=2, T2 (medium) at t=0, and T3 (lowest) at t=0. Each needs some CPU time.

Timing Diagram (described)

Priority high  T1 |          ####                      |
       medium  T2 |     ####.......####                |  (. = pre-empted/waiting)
       low     T3 |#####............................###|
                  +---+----+----+----+----+----+----+--+
   time           0   2    4    6    8   10   12   14

Sequence of events:

1. t=0: T2 and T3 are ready. T2 has higher priority, so it runs; T3 waits.
2. t=2: T1 becomes ready. Being highest priority, it pre-empts T2. T2's context is saved and it moves to the ready state; T1 runs.
3. T1 runs to completion (or blocks).
4. T2 resumes from where it was pre-empted and runs to completion.
5. Finally T3 (lowest priority) gets the CPU and runs.

This guarantees that the most time-critical task (T1) always meets its deadline, which is the goal of real-time scheduling.

Embedded System Design Flow (12 marks)

The embedded design flow is a systematic, top-down process that converts a set of requirements into a deployable product while satisfying tight design metrics.

Flow Diagram (described)

Requirements/Problem Definition
            |
            v
   Specification (functional + non-functional)
            |
            v
   Hardware / Software Partitioning
          /        \
         v          v
  Hardware       Software
  Design         Design  ---- (Hardware-Software Co-design, iterative)
         \          /
          v        v
       Integration
            |
            v
     Testing & Verification
            |
            v
      Final Product / Deployment

Stages

1. Requirement Specification: Capture what the system must do — functional requirements (features, behaviour) and non-functional requirements (timing, power, cost, size, reliability). Produces a clear, unambiguous specification document.
2. Hardware/Software Partitioning: Decide which functions are implemented in hardware (for speed/parallelism) and which in software (for flexibility/lower cost). A critical trade-off step.
3. Hardware–Software Co-design: Develop hardware (processor selection, peripherals, PCB) and software (firmware, drivers, RTOS) concurrently and iteratively, using models/simulation so each influences the other and the partitioning can be refined.
4. Integration: Combine the developed hardware and software; bring up the board, load firmware, and verify that subsystems work together.
5. Testing & Verification: Unit, integration and system testing against the specification — functional tests, timing/real-time tests, stress and field testing. Validate that all requirements and deadlines are met.
6. Final Product: Manufacturing, certification and deployment.

Influence of Design Metrics at Each Stage

• Cost: Drives component selection in partitioning/co-design (cheaper MCU vs FPGA), influences memory size and BOM. Pushes designers toward software solutions on a single MCU.
• Performance: Affects partitioning (move bottleneck functions to hardware), processor speed and clock selection, and is validated during testing.
• Power: Critical for battery/portable devices; influences MCU choice (low-power modes), clock frequency, and is verified in testing. Trades off against performance.
• Time-to-market: Favours reuse of off-the-shelf modules, IP cores and existing software stacks, and encourages parallel co-design to shorten the schedule.

These metrics conflict (e.g. higher performance often raises cost and power), so each stage involves trade-off decisions to reach an optimal balance.

(a) Comparison of I2C, SPI and UART (6 marks)

(b) Interfacing an I2C Temperature Sensor (4 marks)

Interfacing Diagram (described)

        +Vcc
         |
        [R] [R]   <- two pull-up resistors (~4.7k)
         |   |
MCU ----SDA--+---------------+---- SDA  (Temperature Sensor)
MCU ----SCL------+-----------+---- SCL
                 |           |
               GND         GND

• SDA (Serial Data): bidirectional data line carrying address and data bytes.
• SCL (Serial Clock): clock generated by the master to synchronize the transfer.
• Pull-up resistors: I2C lines are open-drain, so external pull-ups (to Vcc) are required to pull the idle line HIGH; devices only pull it LOW.

Sequence to read one byte of temperature data

1. Master issues a START condition (SDA goes LOW while SCL is HIGH).
2. Master sends the 7-bit slave address + R/W = 1 (read).
3. Sensor acknowledges by pulling SDA LOW (ACK).
4. Sensor places one byte of temperature data on SDA; master clocks it in via SCL (MSB first).
5. Master sends NACK (no acknowledge) to indicate it does not want more bytes.
6. Master issues a STOP condition (SDA goes HIGH while SCL is HIGH) to release the bus.

(a) Polling vs Interrupt-driven I/O (4 marks)

(b) Interrupt Service Routine (ISR) (4 marks)

An Interrupt Service Routine (ISR) is a special function automatically executed by the CPU in response to an interrupt. It services the event (e.g. read a byte, clear a flag) and then returns control to the interrupted program.

Steps a microcontroller performs when an interrupt occurs:

1. Complete the current instruction.
2. If the interrupt is enabled and unmasked, acknowledge it and finish the current instruction.
3. Save context — push the Program Counter (and usually status register/key registers) onto the stack so the main program can resume later.
4. Disable further interrupts of equal/lower priority (depending on the controller).
5. Look up the ISR address in the interrupt vector table (a table that maps each interrupt source to its handler's address) and load it into the PC.
6. Execute the ISR to service the device and clear the interrupt flag.
7. On RETI (return-from-interrupt): restore the saved context (pop PC and status), re-enable interrupts, and resume the main program from where it was interrupted.

(a) volatile and const in Embedded C (4 marks)

• volatile: Tells the compiler that a variable's value may change at any time outside the normal program flow, so it must not optimize away or cache accesses — every read/write goes to actual memory. Essential situation: a hardware status register / memory-mapped peripheral or a variable modified inside an ISR but read in main(). Without volatile the compiler may read a stale cached value.

volatile uint8_t *UART_STATUS = (uint8_t*)0x40;
while (!(*UART_STATUS & 0x01)); /* must re-read each time */

• const: Declares a value that the program must not modify; it can be placed in read-only memory (Flash/ROM), saving RAM and catching accidental writes at compile time. Essential situation: storing lookup tables, calibration constants or fixed strings in Flash.

const uint8_t seven_seg[10] = {0x3F,0x06,0x5B,/*...*/};

Note: volatile const uint8_t *reg; is valid — a read-only register the hardware may change.

(b) Embedded C: lower nibble output, upper nibble input (4 marks)

Lower nibble = bits 0–3 (output, 1 in DDR), upper nibble = bits 4–7 (input, 0 in DDR). For an AVR-style MCU:

#include <avr/io.h>

int main(void)
{
    /* DDRB: 1 = output, 0 = input.
       Lower nibble output (0x0F), upper nibble input (0x00). */
    DDRB = 0x0F;          /* 0b00001111 */
    PORTB |= 0xF0;        /* enable pull-ups on input (upper) pins */

    while (1)
    {
        uint8_t in = (PINB & 0xF0); /* read upper nibble (input) */
        in >>= 4;                   /* shift to lower nibble position */
        PORTB = (PORTB & 0xF0) | (in & 0x0F); /* write to output nibble */
    }
    return 0;
}

The & 0xF0 / & 0x0F masks isolate the input and output nibbles so each is handled independently.

Interfacing a DC Motor as an Actuator (6 marks)

A microcontroller I/O pin can only source a few milliamps at logic level (e.g. 5 V, ~20 mA), whereas a DC motor draws hundreds of milliamps to several amps and may run at a different voltage. Therefore the MCU cannot drive the motor directly — a driver circuit is placed between them.

Why a driver circuit (H-bridge / motor-driver IC) is required

• It provides current and voltage amplification, supplying the high current the motor needs from a separate motor supply.
• It isolates and protects the MCU from inductive back-EMF/voltage spikes (with flyback diodes).
• An H-bridge (e.g. L293D, L298N) uses four switching transistors so the motor terminals can be reversed, enabling bidirectional (forward/reverse) rotation.

Why PWM is required

• The MCU controls motor speed by Pulse Width Modulation (PWM) — switching the supply on/off rapidly. The average voltage across the motor is proportional to the duty cycle.
• Higher duty cycle ⇒ higher average voltage ⇒ higher speed; lower duty cycle ⇒ lower speed. PWM gives efficient speed control with little power loss (switches are fully on or off).

Control of speed and direction

MCU --PWM--> EN (enable) pin of driver  -> controls SPEED (duty cycle)
MCU --IN1--> driver input 1
MCU --IN2--> driver input 2            -> controls DIRECTION

• Direction: Set IN1=1, IN2=0 for forward; IN1=0, IN2=1 for reverse; IN1=IN2 to brake/stop.
• Speed: Apply a PWM signal to the enable (EN) pin; varying its duty cycle varies the motor speed.

Microprocessor vs Microcontroller (6 marks)

Major functional blocks integrated inside a typical microcontroller

• CPU core (ALU, control unit, registers)
• Program memory (Flash/ROM) and data memory (RAM), often EEPROM
• Digital I/O ports
• Timers/counters and watchdog timer
• ADC / DAC (analog interface)
• Serial communication peripherals (UART, SPI, I2C)
• Interrupt controller, clock/oscillator circuitry

Why a microcontroller is preferred for embedded applications

Because CPU, memory, and peripherals are integrated on a single chip, it gives lower cost, smaller size, lower power consumption and higher reliability, with fewer external components. This "computer-on-a-chip" exactly suits dedicated, resource-constrained, real-time embedded control tasks.

RTOS Terms (6 marks)

• (a) Latency: The time delay between an event/interrupt occurring and the system beginning to respond to (service) it.
• (b) Jitter: The variation (non-determinism) in the timing or latency of a periodic event from one occurrence to the next — i.e. how much the actual response time deviates from the expected time.
• (c) Deadlock: A situation where two or more tasks are each waiting indefinitely for a resource held by the other, so none can proceed.
• (d) Priority inversion: A condition where a high-priority task is forced to wait for a lower-priority task because the low-priority task holds a shared resource (mutex) the high-priority task needs — and a medium-priority task may further delay it.

How priority inheritance mitigates priority inversion

With priority inheritance, when a low-priority task holds a resource that a higher-priority task is waiting for, the low-priority task temporarily inherits the higher priority of the blocked task. This lets it run without being pre-empted by medium-priority tasks, finish quickly, and release the resource sooner. Once it releases the mutex, it reverts to its original priority and the high-priority task proceeds — bounding the blocking time and preventing unbounded priority inversion.

UART Parameters and Frame Time (6 marks)

Significance of each parameter

• Baud rate: The signalling/symbol rate of the line (bits per second for UART). Both transmitter and receiver must use the same baud rate to sample bits correctly. (9600 bps here.)
• Start bit: A single bit (logic 0) that marks the beginning of a frame; the idle line is high, and the falling edge synchronizes the receiver to start sampling.
• Stop bit: One (or more) bits (logic 1) that mark the end of the frame, ensuring a gap and resynchronization before the next frame.
• Parity bit: An optional bit added for simple error detection, making the total number of 1s even (even parity) or odd (odd parity) so single-bit errors can be detected.

Frame time calculation

Frame size = start + data + parity + stop bits:

$$\text{bits/frame} = 1\ (\text{start}) + 8\ (\text{data}) + 0\ (\text{parity}) + 1\ (\text{stop}) = 10\ \text{bits}$$

Time per bit:

$$T_{bit} = \frac{1}{9600} = 104.17\ \mu s$$

Time to transmit one character frame:

$$T_{frame} = 10 \times T_{bit} = 10 \times 104.17\ \mu s = 1041.7\ \mu s \approx 1.04\ ms$$

Result: One character frame takes about 1.04 ms to transmit.

Analog vs Digital Sensors, ADC, Resolution & Quantization Error (6 marks)

Analog vs Digital sensors

Role of the ADC

A microcontroller is digital and cannot read a continuous analog voltage directly. An Analog-to-Digital Converter (ADC) samples the analog sensor output and converts it into an equivalent N-bit digital number that the MCU can process. It bridges the analog (sensor) world and the digital (processor) world by sampling and quantizing the signal.

Resolution

The resolution is the smallest change in input voltage that produces a one-LSB change at the ADC output. For an N-bit ADC over a reference $V_{ref}$:

$$\text{Resolution} = \frac{V_{ref}}{2^N}$$

e.g. a 10-bit ADC with $V_{ref}=5\,V$: $5/1024 \approx 4.88\ \text{mV}$ per step.

Quantization error

Because a continuous value is mapped to the nearest discrete level, there is an unavoidable rounding error called the quantization error, bounded by:

$$|e_q| \le \frac{1}{2}\,\text{LSB} = \frac{V_{ref}}{2^{N+1}}$$

Higher resolution (more bits) gives smaller step size and smaller quantization error.

Short Notes (any TWO) (4 marks, 2 each)

(a) Watchdog Timer

A watchdog timer (WDT) is a hardware down-counter that resets the microcontroller if the software fails to "kick"/refresh it within a preset time. During normal operation the program periodically clears the timer; if the program hangs or enters an infinite loop (e.g. due to a glitch), the timer overflows and triggers a system reset, returning the embedded system to a known safe state. It is essential for reliability and fault recovery in unattended embedded systems.

(b) Memory-mapped vs Port-mapped I/O

• Memory-mapped I/O: I/O registers share the same address space as memory. The CPU accesses peripherals using ordinary load/store (memory) instructions. Pros: no special I/O instructions, flexible addressing. Cons: consumes part of the memory address space.
• Port-mapped (isolated) I/O: I/O has a separate address space accessed by dedicated instructions (e.g. IN/OUT on x86) with a distinct control line. Pros: full memory space preserved. Cons: needs special instructions and extra control logic. Most microcontrollers (and ARM) use memory-mapped I/O.

(c) RISC vs CISC Architecture

RISC suits low-power, high-throughput embedded MCUs; CISC offers denser code.