BE Computer Engineering (IOE, TU) Embedded System (IOE, CT 655) Question Paper 2079 Nepal

Embedded System: Definition

An embedded system is a dedicated computing system designed to perform one or a few specific functions, often with real-time constraints, embedded as part of a larger device. It combines hardware (a processor, memory, peripherals) and software (firmware) tailored to the application.

Distinguishing Characteristics

• Single/dedicated function – performs a fixed task, unlike a general-purpose PC that runs arbitrary software.
• Real-time operation – must respond within deadlines.
• Resource constrained – limited memory, processing power and energy.
• Reliability and stability – must run continuously without crashing.
• Low power consumption and low unit cost.
• Tightly coupled hardware–software and often no disk/keyboard/monitor.
• Reactive – continuously interacts with its physical environment via sensors/actuators.

Typical Hardware Architecture (Block Diagram)

        +-----------------+
  Power | Power Supply    |----> (Vcc/GND to all blocks)
  ----->+-----------------+
              |
   +----------+-----------+        +-------------+
   |  Processing Unit     |<------>|   Memory    |
   |  (CPU / MCU core,    |        | ROM/Flash   |
   |   ALU, registers)    |        | RAM         |
   +----------+-----------+        +-------------+
              |  (system bus)
   +----------+-----------+
   |  I/O Interfaces      |
   |  (GPIO, ADC/DAC,     |<----> Sensors / Actuators
   |   UART, SPI, I2C,    |       Displays / Network
   |   timers)           |
   +----------------------+

• Processing Unit (CPU/MCU core): fetches, decodes and executes instructions; the ALU performs arithmetic/logic; registers hold operands. It coordinates the whole system.
• Memory subsystem: non-volatile memory (ROM/Flash/EEPROM) stores the program and constants; volatile memory (RAM) holds variables, the stack and runtime data.
• I/O interfaces: connect the processor to the outside world – digital GPIO, analog ADC/DAC, and serial buses (UART, SPI, I2C), timers/counters and interrupt lines link to sensors, actuators and displays.
• Power supply: provides regulated voltage to all blocks; in embedded systems it is a key design concern (battery life, regulation, low-power modes).

Von Neumann vs Harvard Architecture

Suitability for a Microcontroller-Based System

The Harvard architecture (and its modified form) is generally more suitable for microcontrollers because separate program and data buses allow the next instruction to be fetched while the current data is being accessed, giving higher throughput and deterministic, pipelined execution important for real-time tasks. It also naturally separates non-volatile program Flash from volatile data RAM. Hence most MCUs (8051, AVR, PIC) use a Harvard or modified-Harvard design.

(a) Embedded System Design Life Cycle

  Requirement Specification
            |
            v
  System Specification / Modelling
            |
            v
  Architecture Design (HW/SW partition)
            |
            v
  Component / Module Design
            |
        +---+----+
        v        v
   HW Design   SW Design
        |        |
        +---+----+
            v
   System Integration
            |
            v
   Testing & Validation
            |
            v
   Deployment
            |
            v
   Maintenance / Upgrade

• Requirement specification: capture functional and non-functional requirements (function, performance, power, cost).
• System specification & modelling: describe behaviour formally/abstractly.
• Architecture design: define the overall hardware and software structure and partition functionality.
• Component design: detailed design of hardware modules and software modules.
• Integration: combine hardware and software.
• Testing & validation: verify against requirements (unit, integration, system tests).
• Deployment & maintenance: ship the product and provide updates/bug-fixes over its life.

(b) Hardware–Software Co-Design

Hardware–software co-design is the concurrent design of the hardware and software parts of a system so that they are developed and optimized together rather than sequentially. Partitioning decides which functions are implemented in hardware (fast, parallel, power-efficient dedicated logic) versus software (flexible, cheap, easy to modify).

It is critical because the partition directly determines performance, power consumption, cost, flexibility and time-to-market. Putting a function in hardware speeds it up but increases cost and reduces flexibility; putting it in software is cheaper and changeable but may be too slow. A poor partition is hard and expensive to fix late in the cycle.

(c) Influence of Design Metrics

• Power consumption: drives choice of low-power MCU, clock frequency and sleep modes; vital for battery devices.
• Unit cost: pushes toward cheaper processors, less memory and higher integration; important for mass production.
• Performance: may force a faster processor, hardware acceleration or a Harvard/pipelined core.
• Time-to-market: favours reuse, off-the-shelf parts and software flexibility over fully custom hardware.

These metrics often conflict (e.g. performance vs power vs cost), so the designer makes trade-offs to meet the most important constraints of the product.

(a) RTOS and Real-Time Categories

A Real-Time Operating System (RTOS) is an operating system that guarantees that tasks meet their timing deadlines through deterministic scheduling, fast context switching and bounded interrupt latency. Correctness depends not only on the logical result but also on when it is produced.

• Hard real-time: missing a deadline is a total failure / catastrophic. Example: car airbag deployment, pacemaker.
• Firm real-time: occasional missed deadlines are tolerable but the late result is useless (no value after the deadline). Example: frames in a video conference / industrial assembly-line vision.
• Soft real-time: missing a deadline degrades quality but the result still has some value. Example: video streaming, online ticket booking.

(b) Task, Task States and Context Switching

A task (thread/process) is an independent unit of execution scheduled by the RTOS.

Common task states:

• Running – currently executing on the CPU.
• Ready – able to run, waiting for the CPU.
• Blocked/Waiting – waiting for an event/resource/delay.
• Suspended/Dormant – not eligible to run.

Context switching is saving the state (program counter, registers, stack pointer, status flags) of the currently running task and restoring the saved state of the next task, so execution can resume correctly. The saved state is the task's context, stored in its Task Control Block (TCB).

(c) Rate Monotonic Scheduling Analysis

Given:

Total CPU utilization:

$$U = \frac{1}{4} + \frac{2}{6} + \frac{1}{8} = 0.25 + 0.3333 + 0.125 = 0.7083$$

RMS sufficient (Liu & Layland) bound for $n=3$ tasks:

$$U_{bound} = n\left(2^{1/n}-1\right) = 3\left(2^{1/3}-1\right) = 3(1.2599-1) = 0.7798$$

Conclusion: Since $U = 0.7083 \le U_{bound} = 0.7798$, the Liu–Layland test is satisfied, so the task set is schedulable under Rate Monotonic Scheduling (priorities assigned by rate: T1 highest, then T2, then T3). It is also below $U=1$, confirming feasibility.

(a) 8051 Internal Architecture

            +-------------------------------------------+
            |                 8051 CPU                  |
  Internal  |  +-------+   +-----+   +---------------+   |
  ROM/Flash |  |  ALU  |<->| ACC |   | SFRs: PSW,    |   |
  (4KB code)|  +-------+   | B   |   | DPTR,SP,P0-P3 |   |
            |     ^        +-----+   | TMOD,TCON,etc |   |
  Internal  |     |   +----------+   +---------------+   |
  RAM(128B) |<--->|   |   PC     |   | Timers 0/1    |   |
            |     |   +----------+   | Serial(UART)  |   |
            |     |   |Instr.Dec.|   | Interrupt Ctrl|   |
            +-----+---+----------+---+---------------+---+
               |        |          |          |
              P0       P1         P2         P3  (4 x 8-bit I/O ports)

• ALU: performs 8-bit arithmetic and logic operations; works with the Accumulator (A) and B register; sets flags in the PSW.
• Special Function Registers (SFRs): memory-mapped control/status registers such as ACC, B, PSW, SP (stack pointer), DPTR, P0–P3, TMOD, TCON, TH/TL, SCON, IE, IP.
• Four I/O ports (P0–P3): each 8-bit and bit-addressable; provide 32 I/O lines; some pins have alternate functions (serial, interrupts, timer inputs, external memory bus).
• Timers/Counters (Timer0, Timer1): 16-bit, used for delays, event counting, baud-rate generation; configured by TMOD and controlled by TCON.
• Memory organization: 4 KB internal program (ROM) memory (separate from data – Harvard), 128 bytes internal data RAM (register banks, bit-addressable area, scratchpad), expandable up to 64 KB external code and 64 KB external data memory.

(b) Embedded C: Toggle LED on P1.0 using Timer 0, Mode 1

#include <reg51.h>

sbit LED = P1^0;

void delay_T0(void) {
    TMOD &= 0xF0;     // clear Timer0 bits
    TMOD |= 0x01;     // Timer0, Mode 1 (16-bit)
    TH0 = 0x4C;       // reload for ~50 ms @12MHz (50000 counts)
    TL0 = 0x00;
    TR0 = 1;          // start Timer0
    while (TF0 == 0); // wait for overflow
    TR0 = 0;          // stop Timer0
    TF0 = 0;          // clear overflow flag
}

void main(void) {
    while (1) {
        LED = ~LED;   // toggle the LED
        delay_T0();   // timed delay
    }
}

(c) Program Counter and Stack Pointer during a Subroutine Call

On an ACALL/LCALL instruction:

1. The CPU finishes fetching the call instruction, so the PC now holds the address of the next instruction (the return address).
2. The Stack Pointer (SP) is incremented and the low byte of the PC is pushed onto the stack; SP is incremented again and the high byte is pushed. Thus the return address is saved.
3. The PC is loaded with the subroutine's start address and execution continues there.
4. On RET, the high and low bytes are popped back into the PC (SP decremented twice), so execution resumes at the instruction after the call.

Comparison of I2C, SPI and UART

Preferred Applications

• UART: simple point-to-point links such as GPS modules, serial debug console / PC communication, Bluetooth (HC-05) modules.
• SPI: high-speed peripherals such as SD cards, TFT/LCD displays, ADCs and Flash memory.
• I2C: connecting many low-speed on-board chips with few wires, e.g. EEPROMs, RTC (DS1307), and sensors (MPU-6050, BMP280).

I2C Data Transfer

I2C uses two open-drain lines: SDA (data) and SCL (clock). A master generates the clock and initiates all transfers.

Timing Diagram (described)

SDA: ‾‾‾\___X==addr/data==X_/‾ack‾\__X data X /ack\ ___/‾‾‾
           A7..A0 R/W                                  
SCL: ‾‾‾‾‾‾\_/‾\_/‾\_/ ...  /‾\_/‾\_/  ...        /‾‾‾‾‾
      START                ACK                    STOP

• START condition: a high-to-low transition on SDA while SCL is high. It tells all slaves a transfer is beginning and the bus is busy.
• Slave addressing: the master sends a 7-bit slave address followed by a R/W bit (0 = write, 1 = read), MSB first, one bit per SCL clock. The addressed slave recognizes its address.
• Acknowledgement (ACK/NACK): after every 8 bits, the receiver pulls SDA low during the 9th clock = ACK; leaving SDA high = NACK (not acknowledged / end of data / no such device).
• Data transfer: data bytes follow, each acknowledged, MSB first; SDA may only change while SCL is low.
• STOP condition: a low-to-high transition on SDA while SCL is high. It releases the bus.

Why Pull-Up Resistors are Required

The SDA and SCL lines are open-drain (open-collector) outputs: devices can only pull the line low and never actively drive it high. The pull-up resistors (to VCC) provide the logic-high (idle) level and allow the line to return high when no device pulls it low. This also enables wired-AND behaviour needed for multi-master arbitration and clock stretching, and prevents bus contention since multiple devices share the same lines.

(a) Interrupt; Maskable vs Non-Maskable

An interrupt is an asynchronous signal (from hardware or software) that temporarily suspends the normal execution of the processor so that it can service a higher-priority event through an Interrupt Service Routine (ISR), after which it resumes the interrupted program.

• Maskable interrupt: can be enabled or disabled (masked) by software using interrupt-enable bits (e.g. the global interrupt enable / IE register). Used for normal peripheral events. Example: timer/UART interrupts (INTR on 8085).
• Non-maskable interrupt (NMI): cannot be disabled by software; always serviced. Reserved for critical events such as power failure or hardware error / watchdog.

(b) Sequence of Events When an Interrupt is Serviced

1. The peripheral asserts the interrupt request; the CPU completes the current instruction.
2. If the interrupt is enabled and has sufficient priority, the CPU acknowledges it.
3. The processor saves the context – the program counter (return address) and status register (and, in an RTOS/handler, working registers) are pushed onto the stack.
4. The CPU reads the interrupt vector table to obtain the address of the ISR for that interrupt source.
5. The ISR executes, servicing the device and clearing the interrupt flag.
6. On return (RETI/IRET), the saved context is restored (PC and status popped) and the interrupted program resumes exactly where it left off.

The interrupt vector table is a table of ISR addresses indexed by interrupt number, letting the CPU jump directly to the correct handler.

(c) Interrupt Latency, Nesting and Priority

Interrupt latency is the time between the interrupt request being asserted and the first instruction of its ISR beginning to execute. It includes finishing the current instruction, context saving and vector fetch.

• Nesting allows a higher-priority interrupt to interrupt a lower-priority ISR. This reduces latency for high-priority interrupts (they are served promptly) but may increase latency for low-priority ones (they wait longer).
• Priority levels decide which interrupt is served first when several are pending; a higher-priority source gets lower latency. Disabling interrupts (long critical sections) inside an ISR increases worst-case latency, so ISRs should be short.

(a) DC Motor Interfacing with H-Bridge and PWM

A microcontroller GPIO cannot supply the current a DC motor needs and cannot reverse polarity, so an H-bridge driver (e.g. L293D / L298N) is used between the MCU and the motor.

Circuit (described)

        +Vmotor
          |
     +----+----+
     |         |
   [Q1]      [Q2]      <- high-side switches
     |---M----|        M = DC motor across the bridge
   [Q3]      [Q4]      <- low-side switches
     |         |
     +----+----+
          |
         GND

MCU pins -> IN1, IN2 (direction)  ;  EN/PWM pin -> Enable input

• The four transistors form the H-bridge. Turning ON the diagonal pair Q1+Q4 drives current one way (forward); ON Q2+Q3 reverses it (reverse). The MCU sets direction via two control inputs IN1/IN2.
• Flyback/clamp diodes across the transistors protect against the motor's inductive kickback.
• PWM speed control: the MCU applies a PWM signal to the Enable pin. By varying the duty cycle, the average voltage across the motor (and hence its speed) is controlled: $V_{avg} = D \times V_{motor}$, where $D$ is the duty cycle. Higher duty cycle = higher speed.

(b) Analog vs Digital Sensor and the Need for an ADC

The LM35 outputs an analog voltage of 10 mV/°C. A microcontroller's CPU can only process digital (binary) numbers, so an Analog-to-Digital Converter (ADC) is required to sample and quantize the LM35's continuous voltage into a digital value. For example, with a 10-bit ADC and 5 V reference, temperature is computed as $T(^{\circ}C) = \frac{ADC \times 5}{1024 \times 0.01}$. Without the ADC, the MCU could not interpret the analog signal.

(a) volatile and const

• volatile tells the compiler that a variable can change outside the normal program flow (by hardware, an ISR or another thread), so it must not be cached/optimized and must be re-read from memory on every access.

volatile unsigned char *STATUS = (unsigned char *)0x40000000;
while (*STATUS & 0x01); // must re-read the hardware register each time

• const declares a read-only value that the program must not modify; it lets the compiler place data in ROM/Flash and catch accidental writes.

const float PI = 3.14159f;  // stored in Flash, cannot be reassigned

(b) Bit Manipulation in Embedded C

Bit manipulation is important because embedded code constantly reads/writes individual bits of hardware registers (port pins, control/status flags) without disturbing the other bits, saving memory and giving precise control.

PORTB |=  (1 << 3);   // SET bit 3   (OR with mask)
PORTB &= ~(1 << 5);   // CLEAR bit 5 (AND with inverted mask)
PORTB ^=  (1 << 0);   // TOGGLE bit 0 (XOR with mask)

(c) Polling vs Interrupt-Driven I/O

(a) Critical Section and Priority Inversion

A critical section is a region of code that accesses a shared resource (variable, peripheral, buffer) that must be executed by only one task at a time to avoid race conditions; it is protected by a mutex/semaphore or by disabling interrupts.

Priority inversion occurs when a high-priority task is blocked waiting for a resource held by a low-priority task, and a medium-priority task that does not need the resource preempts the low-priority task. The low-priority task cannot finish and release the resource, so the high-priority task is effectively forced to wait behind the medium-priority task — its priority is inverted.

Example: Task H (high) needs a mutex held by Task L (low). Task M (medium) becomes ready and preempts L. L cannot run to release the mutex, so H is blocked indefinitely by M (this famously affected the Mars Pathfinder).

(b) Semaphore for Synchronization and Mutual Exclusion

A semaphore is a kernel object with a counter and two atomic operations: wait/P (take) which decrements the count and blocks if it is zero, and signal/V (give) which increments it and wakes a waiting task.

• Binary semaphore / mutex (count 0 or 1): ensures mutual exclusion — a task takes the semaphore before entering a critical section and gives it on exit, so only one task is inside at a time.
• Counting semaphore: manages a pool of N identical resources, or used for synchronization/signalling (e.g. an ISR gives a semaphore that a task waits on).

(c) Priority Inheritance Protocol

Under the priority inheritance protocol, when a high-priority task blocks on a resource held by a lower-priority task, the low-priority task temporarily inherits the priority of the highest-priority task waiting on that resource. This lets it run (without being preempted by medium-priority tasks), finish the critical section quickly, release the resource, and then return to its original priority. This bounds the blocking time and eliminates unbounded priority inversion.

(a) Microprocessor vs Microcontroller

(b) RISC vs CISC

(c) Watchdog Timer vs General-Purpose Timer

• A general-purpose timer counts clock pulses and is used by the application for delays, event counting, PWM, and baud-rate generation; the program reads/uses its value freely.
• A watchdog timer (WDT) is a special timer that must be periodically reset ("kicked"/fed) by correctly running software. If the software hangs, crashes or enters an infinite loop and fails to reset the WDT before it overflows, the WDT resets the system (or triggers an interrupt).

Importance: Embedded systems often run unattended with no operator to reboot them. The watchdog timer provides automatic recovery from software/hardware faults and lock-ups, greatly improving system reliability and fault tolerance.